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Conference Paper: Acceleration of composite order bilinear pairing on graphics hardware

TitleAcceleration of composite order bilinear pairing on graphics hardware
Authors
Issue Date2012
PublisherSpringer Verlag. The Journal's web site is located at http://springerlink.com/content/105633/
Citation
The 14th International Conference (ICICS 2012), Hong Kong, China, 29-31 October 2012. In Lecture Notes in Computer Science, 2012, v. 7618, p. 341-348 How to Cite?
AbstractRecently, composite-order bilinear pairing has been shown to be useful in many cryptographic constructions. However, it is time-costly to evaluate. This is because the composite order should be at least 1024bit and, hence, the elliptic curve group order n and base field become too large, rendering the bilinear pairing algorithm itself too slow to be practical (e.g., the Miller loop is Ω(n)). Thus, composite-order computation easily becomes the bottleneck of a cryptographic construction, especially, in the case where many pairings need to be evaluated at the same time. The existing solution to this problem that converts composite-order pairings to prime-order ones is only valid for certain constructions. In this paper, we leverage the huge number of threads available on Graphics Processing Units (GPUs) to speed up composite-order pairing computation. We investigate suitable SIMD algorithms for base/extension field, elliptic curve and bilinear pairing computation as well as mapping these algorithms into GPUs with careful considerations. Experimental results show that our method achieves a record of 8.7ms per pairing on a 80bit security level, which is a 20-fold speedup compared to the state-of-the-art CPU implementation. This result also opens the road to adopting higher security levels and using rich-resource parallel platforms, which for example are available in cloud computing. For example, we can achieve a record of 7 × 10 -6 USD per pairing on the Amazon cloud computing environment. © 2012 Springer-Verlag.
DescriptionConference Theme: Information and Communications Security
LNCS v. 7618 entitled: Information and communications security: 14th international conference, ICICS 2012 ... : proceedings
Persistent Identifierhttp://hdl.handle.net/10722/189622
ISSN
2005 Impact Factor: 0.402
2015 SCImago Journal Rankings: 0.252

 

DC FieldValueLanguage
dc.contributor.authorZhang, Yen_US
dc.contributor.authorXue, CJen_US
dc.contributor.authorWong, DSen_US
dc.contributor.authorMamoulis, Nen_US
dc.contributor.authorYiu, SMen_US
dc.date.accessioned2013-09-17T14:50:22Z-
dc.date.available2013-09-17T14:50:22Z-
dc.date.issued2012en_US
dc.identifier.citationThe 14th International Conference (ICICS 2012), Hong Kong, China, 29-31 October 2012. In Lecture Notes in Computer Science, 2012, v. 7618, p. 341-348en_US
dc.identifier.issn0302-9743-
dc.identifier.urihttp://hdl.handle.net/10722/189622-
dc.descriptionConference Theme: Information and Communications Security-
dc.descriptionLNCS v. 7618 entitled: Information and communications security: 14th international conference, ICICS 2012 ... : proceedings-
dc.description.abstractRecently, composite-order bilinear pairing has been shown to be useful in many cryptographic constructions. However, it is time-costly to evaluate. This is because the composite order should be at least 1024bit and, hence, the elliptic curve group order n and base field become too large, rendering the bilinear pairing algorithm itself too slow to be practical (e.g., the Miller loop is Ω(n)). Thus, composite-order computation easily becomes the bottleneck of a cryptographic construction, especially, in the case where many pairings need to be evaluated at the same time. The existing solution to this problem that converts composite-order pairings to prime-order ones is only valid for certain constructions. In this paper, we leverage the huge number of threads available on Graphics Processing Units (GPUs) to speed up composite-order pairing computation. We investigate suitable SIMD algorithms for base/extension field, elliptic curve and bilinear pairing computation as well as mapping these algorithms into GPUs with careful considerations. Experimental results show that our method achieves a record of 8.7ms per pairing on a 80bit security level, which is a 20-fold speedup compared to the state-of-the-art CPU implementation. This result also opens the road to adopting higher security levels and using rich-resource parallel platforms, which for example are available in cloud computing. For example, we can achieve a record of 7 × 10 -6 USD per pairing on the Amazon cloud computing environment. © 2012 Springer-Verlag.-
dc.languageengen_US
dc.publisherSpringer Verlag. The Journal's web site is located at http://springerlink.com/content/105633/-
dc.relation.ispartofLecture Notes in Computer Scienceen_US
dc.rightsThe original publication is available at www.springerlink.com-
dc.rightsCreative Commons: Attribution 3.0 Hong Kong License-
dc.titleAcceleration of composite order bilinear pairing on graphics hardwareen_US
dc.typeConference_Paperen_US
dc.identifier.emailZhang, Y: yezhang4@hku.hken_US
dc.identifier.emailMamoulis, N: nikos@cs.hku.hken_US
dc.identifier.emailYiu, SM: smyiu@cs.hku.hken_US
dc.identifier.authorityMamoulis, N=rp00155en_US
dc.identifier.authorityYiu, SM=rp00207en_US
dc.description.naturepostprint-
dc.identifier.doi10.1007/978-3-642-34129-8_31-
dc.identifier.scopuseid_2-s2.0-84868328399-
dc.identifier.hkuros221083en_US
dc.identifier.volume7618-
dc.identifier.spage341en_US
dc.identifier.epage348en_US
dc.publisher.placeGermany-
dc.customcontrol.immutablesml 150123-

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