File Download

There are no files associated with this item.

  Links for fulltext
     (May Require Subscription)
Supplementary

Article: CLOCKING SCHEMES FOR HIGH-SPEED DIGITAL SYSTEMS.

TitleCLOCKING SCHEMES FOR HIGH-SPEED DIGITAL SYSTEMS.
Authors
Issue Date1986
PublisherI E E E. The Journal's web site is located at http://www.computer.org/tc
Citation
Ieee Transactions On Computers, 1986, v. C-35 n. 10, p. 880-895 How to Cite?
AbstractBased on a worst case analysis, clocking schemes for high-performance systems are analyzed. These are 1- and 2-phase systems using simple clocked latches, and 1-phase systems using edge-triggered D-flip-flops. Within these categories (any of which may be preferable in a given situation), it is shown how optimal tradeoffs can be made by appropriately choosing the parameters of the clocking system as a function of the technology parameters. The tradeoffs involve the clock period (which determines the data rate), and the tolerances that must be enforced on the propagation delays through the logic. Clock-pulse edge tolerances are shown to be an important factor. It is seen that, for systems using latches, their detrimental effects on the clock period can be converted to tighter bounds on the short-path delays by allowing D changes to lag behind the leading edges of the clock pulses and by using wider clock pulses or, in the case of 2-phase systems, by overlapping the clock pulses.
Persistent Identifierhttp://hdl.handle.net/10722/176308
ISSN
2015 Impact Factor: 1.723
2015 SCImago Journal Rankings: 0.924

 

DC FieldValueLanguage
dc.contributor.authorUnger, Stephen Hen_US
dc.contributor.authorTan, ChungJenen_US
dc.date.accessioned2012-11-26T09:08:44Z-
dc.date.available2012-11-26T09:08:44Z-
dc.date.issued1986en_US
dc.identifier.citationIeee Transactions On Computers, 1986, v. C-35 n. 10, p. 880-895en_US
dc.identifier.issn0018-9340en_US
dc.identifier.urihttp://hdl.handle.net/10722/176308-
dc.description.abstractBased on a worst case analysis, clocking schemes for high-performance systems are analyzed. These are 1- and 2-phase systems using simple clocked latches, and 1-phase systems using edge-triggered D-flip-flops. Within these categories (any of which may be preferable in a given situation), it is shown how optimal tradeoffs can be made by appropriately choosing the parameters of the clocking system as a function of the technology parameters. The tradeoffs involve the clock period (which determines the data rate), and the tolerances that must be enforced on the propagation delays through the logic. Clock-pulse edge tolerances are shown to be an important factor. It is seen that, for systems using latches, their detrimental effects on the clock period can be converted to tighter bounds on the short-path delays by allowing D changes to lag behind the leading edges of the clock pulses and by using wider clock pulses or, in the case of 2-phase systems, by overlapping the clock pulses.en_US
dc.languageengen_US
dc.publisherI E E E. The Journal's web site is located at http://www.computer.org/tcen_US
dc.relation.ispartofIEEE Transactions on Computersen_US
dc.titleCLOCKING SCHEMES FOR HIGH-SPEED DIGITAL SYSTEMS.en_US
dc.typeArticleen_US
dc.identifier.emailTan, ChungJen: ctan@eti.hku.hken_US
dc.identifier.authorityTan, ChungJen=rp01379en_US
dc.description.naturelink_to_subscribed_fulltexten_US
dc.identifier.scopuseid_2-s2.0-0022795057en_US
dc.identifier.volumeC-35en_US
dc.identifier.issue10en_US
dc.identifier.spage880en_US
dc.identifier.epage895en_US
dc.publisher.placeUnited Statesen_US
dc.identifier.scopusauthoridUnger, Stephen H=7102821063en_US
dc.identifier.scopusauthoridTan, ChungJen=22981715400en_US

Export via OAI-PMH Interface in XML Formats


OR


Export to Other Non-XML Formats