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Conference Paper: A model for peak matrix performance on FPGAs

TitleA model for peak matrix performance on FPGAs
Authors
KeywordsPeak Performance
Model
Matrix
Fpga
Issue Date2011
PublisherIEEE Computer Society. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/conhome.jsp?punumber=1000289
Citation
The 19th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM 2011), Salt Lake City, UT., 1-3 May 2011. In Conference Proceedings, 2011, p. 251-251 How to Cite?
AbstractComputations involving matrices form the kernel of a large spectrum of computationally demanding applications for which FPGAs have actively been utilized as accelerators. The performances of such matrix operations on FPGAs are related to underlying architectural parameters such as computational resources, memory and I/O bandwidth. A model that gives bounds on the peak performance of matrix-vector and matrix-matrix multiplication operations on FPGAs based on these parameters is presented. The architecture and efficiency of existing implementations are compared against the model. Future trends in matrix performance on FPGA devices are estimated based on the performance model and system parameters from the past decade. © 2011 IEEE.
Persistent Identifierhttp://hdl.handle.net/10722/158706
ISBN
ISI Accession Number ID

 

DC FieldValueLanguage
dc.contributor.authorLin, CYen_US
dc.contributor.authorSo, HKHen_US
dc.contributor.authorLeong, PHWen_US
dc.date.accessioned2012-08-08T09:00:58Z-
dc.date.available2012-08-08T09:00:58Z-
dc.date.issued2011en_US
dc.identifier.citationThe 19th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM 2011), Salt Lake City, UT., 1-3 May 2011. In Conference Proceedings, 2011, p. 251-251en_US
dc.identifier.isbn978-0-7695-4301-7-
dc.identifier.urihttp://hdl.handle.net/10722/158706-
dc.description.abstractComputations involving matrices form the kernel of a large spectrum of computationally demanding applications for which FPGAs have actively been utilized as accelerators. The performances of such matrix operations on FPGAs are related to underlying architectural parameters such as computational resources, memory and I/O bandwidth. A model that gives bounds on the peak performance of matrix-vector and matrix-matrix multiplication operations on FPGAs based on these parameters is presented. The architecture and efficiency of existing implementations are compared against the model. Future trends in matrix performance on FPGA devices are estimated based on the performance model and system parameters from the past decade. © 2011 IEEE.en_US
dc.languageengen_US
dc.publisherIEEE Computer Society. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/conhome.jsp?punumber=1000289-
dc.relation.ispartofAnnual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM)en_US
dc.rightsAnnual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM). Copyright © IEEE Computer Society.-
dc.rights©2011 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.-
dc.rightsCreative Commons: Attribution 3.0 Hong Kong License-
dc.subjectPeak Performanceen_US
dc.subjectModelen_US
dc.subjectMatrixen_US
dc.subjectFpgaen_US
dc.titleA model for peak matrix performance on FPGAsen_US
dc.typeConference_Paperen_US
dc.identifier.emailSo, HKH: skhay@hkucc.hku.hken_US
dc.identifier.authoritySo, HKH=rp00169en_US
dc.description.naturepublished_or_final_versionen_US
dc.identifier.doi10.1109/FCCM.2011.51en_US
dc.identifier.scopuseid_2-s2.0-79958737506en_US
dc.identifier.hkuros236892-
dc.identifier.spage251en_US
dc.identifier.epage251-
dc.identifier.isiWOS:000298664800044-
dc.publisher.placeUnited States-
dc.identifier.scopusauthoridLeong, PHW=7005928205en_US
dc.identifier.scopusauthoridSo, HKH=10738896800en_US
dc.identifier.scopusauthoridLin, CY=35177986900en_US
dc.customcontrol.immutablesml 140902-

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