Interconnect performance and scaling strategy for the 22 nm node and beyond

Abstract

After four decades of continuous scaling on the CMOS technology, many innovations have been realized for improving interconnects RC performance since the emergence of copper. However, wire resistance has become a dominant factor on interconnect RC performance at the 22nm node. Optimization of metal aspect ratio and barrier thickness are important directions for mitigating the increase of wire resistance. In addition to reducing the dielectric constant of the ULK MD, reducing the dielectric constant of the copper capping layer and the transitional layer of the ULK MD are approaches for lowering the parasitic capacitance. In order to further boost interconnect performance, an air-gap integration is an option for reducing the capacitance without scaling metal thickness. Therefore, conventional scaling can be extended to the next generation. © 2009 Materials Research Society.