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Conference Paper: A 0.9V 2.7μW small-area 100μs+ analog CMOS tunable-delay circuit utilizing miller effect
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TitleA 0.9V 2.7μW small-area 100μs+ analog CMOS tunable-delay circuit utilizing miller effect
 
AuthorsNg, DCW2
Wong, N1
Kwong, DKK2
 
Issue Date2008
 
Citation2008 Ieee International Conference On Electron Devices And Solid-State Circuits, Edssc, 2008 [How to Cite?]
DOI: http://dx.doi.org/10.1109/EDSSC.2008.4760685
 
AbstractWe report a novel analog delay circuit based on Miller effect that features small die area and tunable delay in the order of 100μs, without using any external component. The delay time can be tuned by varying the biasing current, capacitor sizes, transconductance of the gain-stage transistor and the corresponding output impedances. The turn-on threshold of the delay circuit can also be raised, as required in some applications, by utilizing the body effect of the input transistors. The circuit has a very low startup voltage (≈0.9V) and consumes a very low power (≈2.7μW) in a standard 1 μm pure CMOS process with Vtn ≈ 0.65V and Vtp ≈ 0.8V at 25°C. Circuit operations are elaborated and its function is verified by simulation and silicon measurement. © 2008 IEEE.
 
DOIhttp://dx.doi.org/10.1109/EDSSC.2008.4760685
 
ReferencesReferences in Scopus
 
DC FieldValue
dc.contributor.authorNg, DCW
 
dc.contributor.authorWong, N
 
dc.contributor.authorKwong, DKK
 
dc.date.accessioned2012-08-08T09:00:21Z
 
dc.date.available2012-08-08T09:00:21Z
 
dc.date.issued2008
 
dc.description.abstractWe report a novel analog delay circuit based on Miller effect that features small die area and tunable delay in the order of 100μs, without using any external component. The delay time can be tuned by varying the biasing current, capacitor sizes, transconductance of the gain-stage transistor and the corresponding output impedances. The turn-on threshold of the delay circuit can also be raised, as required in some applications, by utilizing the body effect of the input transistors. The circuit has a very low startup voltage (≈0.9V) and consumes a very low power (≈2.7μW) in a standard 1 μm pure CMOS process with Vtn ≈ 0.65V and Vtp ≈ 0.8V at 25°C. Circuit operations are elaborated and its function is verified by simulation and silicon measurement. © 2008 IEEE.
 
dc.description.natureLink_to_subscribed_fulltext
 
dc.identifier.citation2008 Ieee International Conference On Electron Devices And Solid-State Circuits, Edssc, 2008 [How to Cite?]
DOI: http://dx.doi.org/10.1109/EDSSC.2008.4760685
 
dc.identifier.doihttp://dx.doi.org/10.1109/EDSSC.2008.4760685
 
dc.identifier.scopuseid_2-s2.0-63549132360
 
dc.identifier.urihttp://hdl.handle.net/10722/158582
 
dc.languageeng
 
dc.relation.ispartof2008 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC
 
dc.relation.referencesReferences in Scopus
 
dc.titleA 0.9V 2.7μW small-area 100μs+ analog CMOS tunable-delay circuit utilizing miller effect
 
dc.typeConference_Paper
 
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Author Affiliations
  1. The University of Hong Kong
  2. Hong Kong Applied Science and Technology Research Institute