Conference Paper: A 0.9V 2.7μW small-area 100μs+ analog CMOS tunable-delay circuit utilizing miller effect
| Title | A 0.9V 2.7μW small-area 100μs+ analog CMOS tunable-delay circuit utilizing miller effect |
|---|---|
| Authors | Ng, DCW2 Wong, N1 Kwong, DKK2 |
| Issue Date | 2008 |
| Citation | 2008 Ieee International Conference On Electron Devices And Solid-State Circuits, Edssc, 2008 [How to Cite?] DOI: http://dx.doi.org/10.1109/EDSSC.2008.4760685 |
| Abstract | We report a novel analog delay circuit based on Miller effect that features small die area and tunable delay in the order of 100μs, without using any external component. The delay time can be tuned by varying the biasing current, capacitor sizes, transconductance of the gain-stage transistor and the corresponding output impedances. The turn-on threshold of the delay circuit can also be raised, as required in some applications, by utilizing the body effect of the input transistors. The circuit has a very low startup voltage (≈0.9V) and consumes a very low power (≈2.7μW) in a standard 1 μm pure CMOS process with Vtn ≈ 0.65V and Vtp ≈ 0.8V at 25°C. Circuit operations are elaborated and its function is verified by simulation and silicon measurement. © 2008 IEEE. |
| DOI | http://dx.doi.org/10.1109/EDSSC.2008.4760685 |
| References | References in Scopus |
| dc.contributor.author | Ng, DCW |
|---|---|
| dc.contributor.author | Wong, N |
| dc.contributor.author | Kwong, DKK |
| dc.date.accessioned | 2012-08-08T09:00:21Z |
| dc.date.available | 2012-08-08T09:00:21Z |
| dc.date.issued | 2008 |
| dc.description.abstract | We report a novel analog delay circuit based on Miller effect that features small die area and tunable delay in the order of 100μs, without using any external component. The delay time can be tuned by varying the biasing current, capacitor sizes, transconductance of the gain-stage transistor and the corresponding output impedances. The turn-on threshold of the delay circuit can also be raised, as required in some applications, by utilizing the body effect of the input transistors. The circuit has a very low startup voltage (≈0.9V) and consumes a very low power (≈2.7μW) in a standard 1 μm pure CMOS process with Vtn ≈ 0.65V and Vtp ≈ 0.8V at 25°C. Circuit operations are elaborated and its function is verified by simulation and silicon measurement. © 2008 IEEE. |
| dc.description.nature | Link_to_subscribed_fulltext |
| dc.identifier.citation | 2008 Ieee International Conference On Electron Devices And Solid-State Circuits, Edssc, 2008 [How to Cite?] DOI: http://dx.doi.org/10.1109/EDSSC.2008.4760685 |
| dc.identifier.doi | http://dx.doi.org/10.1109/EDSSC.2008.4760685 |
| dc.identifier.scopus | eid_2-s2.0-63549132360 |
| dc.identifier.uri | http://hdl.handle.net/10722/158582 |
| dc.language | eng |
| dc.relation.ispartof | 2008 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC |
| dc.relation.references | References in Scopus |
| dc.title | A 0.9V 2.7μW small-area 100μs+ analog CMOS tunable-delay circuit utilizing miller effect |
| dc.type | Conference_Paper |
Author Affiliations
- The University of Hong Kong
- Hong Kong Applied Science and Technology Research Institute