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Conference Paper: Gate leakage properties of MOS devices with TriLayer high-k gate dielectric

TitleGate leakage properties of MOS devices with TriLayer high-k gate dielectric
Authors
Issue Date2006
Citation
2005 Ieee Conference On Electron Devices And Solid-State Circuits, Edssc, 2006, p. 695-698 How to Cite?
AbstractGate leakage of deep-submicron MOSFET with stack high-k dielectrics as gate insulator is studied by building a model of tunneling current. Validity of the model is checked for MOSFET's with SiO 2 and high-k dielectric material as gate dielectric respectively, and simulated results exhibit good agreement with experimental data. The model is successfully used for a tri-layer gate-dielectric structure of HfON/HfO 2/HfSiON with a U-shape nitrogen profile and a Si/SiO 2-like interface, which is proposed to solve the problems of boron diffusion into channel region and high interface-state density between Si and high-k dielectric. By using the model, the optimum structural parameters of the tri-layer dielectric can be determined. For example, for an equivalent oxide thickness of 2.0 nm, the tri-layer gate-dielectric MOS capacitor with 0.3-nm HfON, 0.5- nm HfO 2 and 1.2-nm HfSiON exhibits the lowest gate leakage. ©2005 IEEE.
Persistent Identifierhttp://hdl.handle.net/10722/158516
References

 

DC FieldValueLanguage
dc.contributor.authorChen, WBen_US
dc.contributor.authorXu, JPen_US
dc.contributor.authorLai, PTen_US
dc.contributor.authorLi, YPen_US
dc.contributor.authorXu, SGen_US
dc.date.accessioned2012-08-08T09:00:02Z-
dc.date.available2012-08-08T09:00:02Z-
dc.date.issued2006en_US
dc.identifier.citation2005 Ieee Conference On Electron Devices And Solid-State Circuits, Edssc, 2006, p. 695-698en_US
dc.identifier.urihttp://hdl.handle.net/10722/158516-
dc.description.abstractGate leakage of deep-submicron MOSFET with stack high-k dielectrics as gate insulator is studied by building a model of tunneling current. Validity of the model is checked for MOSFET's with SiO 2 and high-k dielectric material as gate dielectric respectively, and simulated results exhibit good agreement with experimental data. The model is successfully used for a tri-layer gate-dielectric structure of HfON/HfO 2/HfSiON with a U-shape nitrogen profile and a Si/SiO 2-like interface, which is proposed to solve the problems of boron diffusion into channel region and high interface-state density between Si and high-k dielectric. By using the model, the optimum structural parameters of the tri-layer dielectric can be determined. For example, for an equivalent oxide thickness of 2.0 nm, the tri-layer gate-dielectric MOS capacitor with 0.3-nm HfON, 0.5- nm HfO 2 and 1.2-nm HfSiON exhibits the lowest gate leakage. ©2005 IEEE.en_US
dc.languageengen_US
dc.relation.ispartof2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSCen_US
dc.titleGate leakage properties of MOS devices with TriLayer high-k gate dielectricen_US
dc.typeConference_Paperen_US
dc.identifier.emailLai, PT:laip@eee.hku.hken_US
dc.identifier.authorityLai, PT=rp00130en_US
dc.description.naturelink_to_subscribed_fulltexten_US
dc.identifier.doi10.1109/EDSSC.2005.1635370en_US
dc.identifier.scopuseid_2-s2.0-43549125059en_US
dc.relation.referenceshttp://www.scopus.com/mlt/select.url?eid=2-s2.0-43549125059&selection=ref&src=s&origin=recordpageen_US
dc.identifier.spage695en_US
dc.identifier.epage698en_US
dc.identifier.scopusauthoridChen, WB=51563508300en_US
dc.identifier.scopusauthoridXu, JP=35754128700en_US
dc.identifier.scopusauthoridLai, PT=7202946460en_US
dc.identifier.scopusauthoridLi, YP=47661368400en_US
dc.identifier.scopusauthoridXu, SG=14055300000en_US

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