Standard cell design with regularly-placed contacts and gates

Abstract

The layout strategies of standard cells with regularly-placed contacts and gates are studied. The regular placement enables more effective use of resolution enhancement technologies, which in turn allows a reduction of critical dimensions. Although regular placement of contacts and gates adds restrictions during cell layout, the overall circuit area can be made smaller and the number of extra masks and exposures can be kept to the lowest by careful selection of the grid pitch, using template-trim lithography method, allowing random contact placement in the vertical direction, and using rectangular rather than square contacts. Three different fabrication-friendly layouts are compared in this study. The average area change of 64 standard cells in a 130 nm library range from -4.2% to -1.2% with the 3 fabrication-friendly layout approaches. The area change of 5 test circuits using the 3 approaches range from -5.4% to +2.6%. Power consumption and intrinsic delay also improve with the decrease in circuits area, which is verified with the examination results.