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Conference Paper: Standard cell design with regularly-placed contacts and gates

TitleStandard cell design with regularly-placed contacts and gates
Authors
KeywordsCircuit Delay
Fabrication-Friendly Layout
Low-K1 Lithography
Multiple Exposures
Power Consumption
Resolution Enhancement Technologies
Standard Cells
Template Lithography
Issue Date2004
PublisherSPIE - International Society for Optical Engineering. The Journal's web site is located at http://spie.org/x1848.xml
Citation
The 2nd Design and Process Integration for Microelectronic Manufacturing Conference, Santa Clara, CA., 22 February 2004. In Proceedings of SPIE, 2004, v. 5379, p. 55-66 How to Cite?
AbstractThe layout strategies of standard cells with regularly-placed contacts and gates are studied. The regular placement enables more effective use of resolution enhancement technologies, which in turn allows a reduction of critical dimensions. Although regular placement of contacts and gates adds restrictions during cell layout, the overall circuit area can be made smaller and the number of extra masks and exposures can be kept to the lowest by careful selection of the grid pitch, using template-trim lithography method, allowing random contact placement in the vertical direction, and using rectangular rather than square contacts. Three different fabrication-friendly layouts are compared in this study. The average area change of 64 standard cells in a 130 nm library range from -4.2% to -1.2% with the 3 fabrication-friendly layout approaches. The area change of 5 test circuits using the 3 approaches range from -5.4% to +2.6%. Power consumption and intrinsic delay also improve with the decrease in circuits area, which is verified with the examination results.
Persistent Identifierhttp://hdl.handle.net/10722/158427
ISSN
References

 

DC FieldValueLanguage
dc.contributor.authorWang, Jen_US
dc.contributor.authorWong, AKen_US
dc.contributor.authorLam, EYen_US
dc.date.accessioned2012-08-08T08:59:34Z-
dc.date.available2012-08-08T08:59:34Z-
dc.date.issued2004en_US
dc.identifier.citationThe 2nd Design and Process Integration for Microelectronic Manufacturing Conference, Santa Clara, CA., 22 February 2004. In Proceedings of SPIE, 2004, v. 5379, p. 55-66en_US
dc.identifier.issn0277-786Xen_US
dc.identifier.urihttp://hdl.handle.net/10722/158427-
dc.description.abstractThe layout strategies of standard cells with regularly-placed contacts and gates are studied. The regular placement enables more effective use of resolution enhancement technologies, which in turn allows a reduction of critical dimensions. Although regular placement of contacts and gates adds restrictions during cell layout, the overall circuit area can be made smaller and the number of extra masks and exposures can be kept to the lowest by careful selection of the grid pitch, using template-trim lithography method, allowing random contact placement in the vertical direction, and using rectangular rather than square contacts. Three different fabrication-friendly layouts are compared in this study. The average area change of 64 standard cells in a 130 nm library range from -4.2% to -1.2% with the 3 fabrication-friendly layout approaches. The area change of 5 test circuits using the 3 approaches range from -5.4% to +2.6%. Power consumption and intrinsic delay also improve with the decrease in circuits area, which is verified with the examination results.en_US
dc.languageengen_US
dc.publisherSPIE - International Society for Optical Engineering. The Journal's web site is located at http://spie.org/x1848.xmlen_US
dc.relation.ispartofProceedings of SPIE - The International Society for Optical Engineeringen_US
dc.subjectCircuit Delayen_US
dc.subjectFabrication-Friendly Layouten_US
dc.subjectLow-K1 Lithographyen_US
dc.subjectMultiple Exposuresen_US
dc.subjectPower Consumptionen_US
dc.subjectResolution Enhancement Technologiesen_US
dc.subjectStandard Cellsen_US
dc.subjectTemplate Lithographyen_US
dc.titleStandard cell design with regularly-placed contacts and gatesen_US
dc.typeConference_Paperen_US
dc.identifier.emailLam, EY:elam@eee.hku.hken_US
dc.identifier.authorityLam, EY=rp00131en_US
dc.description.naturelink_to_subscribed_fulltexten_US
dc.identifier.doi10.1117/12.534538en_US
dc.identifier.scopuseid_2-s2.0-2942640095en_US
dc.identifier.hkuros88835-
dc.relation.referenceshttp://www.scopus.com/mlt/select.url?eid=2-s2.0-2942640095&selection=ref&src=s&origin=recordpageen_US
dc.identifier.volume5379en_US
dc.identifier.spage55en_US
dc.identifier.epage66en_US
dc.publisher.placeUnited Statesen_US
dc.identifier.scopusauthoridWang, J=8716933500en_US
dc.identifier.scopusauthoridWong, AK=7403147663en_US
dc.identifier.scopusauthoridLam, EY=7102890004en_US
dc.customcontrol.immutablesml 151002 - merged-

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