File Download

There are no files associated with this item.

  Links for fulltext
     (May Require Subscription)
Supplementary

Conference Paper: Effective BIST scheme for delay testing

TitleEffective BIST scheme for delay testing
Authors
Issue Date1998
Citation
Proceedings - Ieee International Symposium On Circuits And Systems, 1998, v. 2, p. 288-291 How to Cite?
AbstractThis paper presents a BIST scheme for the detection of path delay faults. It differs from the traditional BIST schemes which aim at stuck-at faults by offering higher capability of two-pattern generation. The TPG scheme produces test sequences having exactly the same robust path delay fault coverage as single-input-change test sequences. By determining nonadjacent inputs, the reduction of both test length and area overhead can be achieved. Signature analysis under path delay fault is also discussed. Based on true-value simulation, error patterns under path delay fault model were obtained and were used in aliasing estimation.
Persistent Identifierhttp://hdl.handle.net/10722/158247
ISSN

 

DC FieldValueLanguage
dc.contributor.authorLi, Xiaoweien_US
dc.contributor.authorCheung, Paul YSen_US
dc.date.accessioned2012-08-08T08:58:43Z-
dc.date.available2012-08-08T08:58:43Z-
dc.date.issued1998en_US
dc.identifier.citationProceedings - Ieee International Symposium On Circuits And Systems, 1998, v. 2, p. 288-291en_US
dc.identifier.issn0271-4310en_US
dc.identifier.urihttp://hdl.handle.net/10722/158247-
dc.description.abstractThis paper presents a BIST scheme for the detection of path delay faults. It differs from the traditional BIST schemes which aim at stuck-at faults by offering higher capability of two-pattern generation. The TPG scheme produces test sequences having exactly the same robust path delay fault coverage as single-input-change test sequences. By determining nonadjacent inputs, the reduction of both test length and area overhead can be achieved. Signature analysis under path delay fault is also discussed. Based on true-value simulation, error patterns under path delay fault model were obtained and were used in aliasing estimation.en_US
dc.languageengen_US
dc.relation.ispartofProceedings - IEEE International Symposium on Circuits and Systemsen_US
dc.titleEffective BIST scheme for delay testingen_US
dc.typeConference_Paperen_US
dc.identifier.emailCheung, Paul YS:paul.cheung@hku.hken_US
dc.identifier.authorityCheung, Paul YS=rp00077en_US
dc.description.naturelink_to_subscribed_fulltexten_US
dc.identifier.scopuseid_2-s2.0-0031635675en_US
dc.identifier.volume2en_US
dc.identifier.spage288en_US
dc.identifier.epage291en_US
dc.identifier.scopusauthoridLi, Xiaowei=8228906100en_US
dc.identifier.scopusauthoridCheung, Paul YS=7202595335en_US

Export via OAI-PMH Interface in XML Formats


OR


Export to Other Non-XML Formats