Programmable image processing system using FPGA

Abstract

Real-time image processing usually requires enormous throughput rate and huge amount of operations. Parallel processing in form of specialized hardware or multiprocessing are therefore indispensable. This paper describes a flexible programmable image processing system using Field Programmable Gate Array (FPGA). The logic cell nature of current available FPGA is most suitable for performing real-time bit-level image processing operations using bit-level systolic concept. Here, we proposed a flexible architecture, PIPS, for the integration of these programmable hardware and digital signal processors (DSP) to handle bit-level as well as arithmetic operations found in many image processing applications. The versatility of the system is demonstrated for the implementation of a 1D median filter.