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Conference Paper: Programmable image processing system using FPGA

TitleProgrammable image processing system using FPGA
Authors
Issue Date1994
Citation
Proceedings - Ieee International Symposium On Circuits And Systems, 1994, v. 2, p. 125-128 How to Cite?
AbstractReal-time image processing usually requires enormous throughput rate and huge amount of operations. Parallel processing in form of specialized hardware or multiprocessing are therefore indispensable. This paper describes a flexible programmable image processing system using Field Programmable Gate Array (FPGA). The logic cell nature of current available FPGA is most suitable for performing real-time bit-level image processing operations using bit-level systolic concept. Here, we proposed a flexible architecture, PIPS, for the integration of these programmable hardware and digital signal processors (DSP) to handle bit-level as well as arithmetic operations found in many image processing applications. The versatility of the system is demonstrated for the implementation of a 1D median filter.
Persistent Identifierhttp://hdl.handle.net/10722/158145
ISSN

 

DC FieldValueLanguage
dc.contributor.authorChan, SCen_US
dc.contributor.authorNgai, HOen_US
dc.contributor.authorHo, KLen_US
dc.date.accessioned2012-08-08T08:58:15Z-
dc.date.available2012-08-08T08:58:15Z-
dc.date.issued1994en_US
dc.identifier.citationProceedings - Ieee International Symposium On Circuits And Systems, 1994, v. 2, p. 125-128en_US
dc.identifier.issn0271-4310en_US
dc.identifier.urihttp://hdl.handle.net/10722/158145-
dc.description.abstractReal-time image processing usually requires enormous throughput rate and huge amount of operations. Parallel processing in form of specialized hardware or multiprocessing are therefore indispensable. This paper describes a flexible programmable image processing system using Field Programmable Gate Array (FPGA). The logic cell nature of current available FPGA is most suitable for performing real-time bit-level image processing operations using bit-level systolic concept. Here, we proposed a flexible architecture, PIPS, for the integration of these programmable hardware and digital signal processors (DSP) to handle bit-level as well as arithmetic operations found in many image processing applications. The versatility of the system is demonstrated for the implementation of a 1D median filter.en_US
dc.languageengen_US
dc.relation.ispartofProceedings - IEEE International Symposium on Circuits and Systemsen_US
dc.titleProgrammable image processing system using FPGAen_US
dc.typeConference_Paperen_US
dc.identifier.emailChan, SC:scchan@eee.hku.hken_US
dc.identifier.emailHo, KL:klho@eee.hku.hken_US
dc.identifier.authorityChan, SC=rp00094en_US
dc.identifier.authorityHo, KL=rp00117en_US
dc.description.naturelink_to_subscribed_fulltexten_US
dc.identifier.scopuseid_2-s2.0-0028594363en_US
dc.identifier.volume2en_US
dc.identifier.spage125en_US
dc.identifier.epage128en_US
dc.identifier.scopusauthoridChan, SC=13310287100en_US
dc.identifier.scopusauthoridNgai, HO=6602732278en_US
dc.identifier.scopusauthoridHo, KL=7403581592en_US

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