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Conference Paper: Primitive interval labelled net model and timing modelling of logic circuits
Title | Primitive interval labelled net model and timing modelling of logic circuits |
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Authors | |
Issue Date | 1991 |
Citation | Proceedings - Ieee International Symposium On Circuits And Systems, 1991, v. 2, p. 934-937 How to Cite? |
Abstract | A reduced version of the interval labeled net model called the primitive interval labeled net model is introduced. By incorporating a projection operator which is based on applying the if-then clause representation of Boolean functions to multivalued logic circuits, the primitive interval labeled net model is powerful enough to model multivalued logic circuits with timing information and all properties of the interval labeled net. This facilitates a better implementation of the verification and simulation than that using the former net model. The number of token types is reduced from four to two. This model involves simpler types of net adjacency relations. The power of the approach is demonstrated by a logic circuit implemented using logic gates with different rise and fall times. |
Persistent Identifier | http://hdl.handle.net/10722/158092 |
ISSN | 2023 SCImago Journal Rankings: 0.307 |
DC Field | Value | Language |
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dc.contributor.author | Chiu, Peter PK | en_US |
dc.contributor.author | Cheung, YS | en_US |
dc.date.accessioned | 2012-08-08T08:58:02Z | - |
dc.date.available | 2012-08-08T08:58:02Z | - |
dc.date.issued | 1991 | en_US |
dc.identifier.citation | Proceedings - Ieee International Symposium On Circuits And Systems, 1991, v. 2, p. 934-937 | en_US |
dc.identifier.issn | 0271-4310 | en_US |
dc.identifier.uri | http://hdl.handle.net/10722/158092 | - |
dc.description.abstract | A reduced version of the interval labeled net model called the primitive interval labeled net model is introduced. By incorporating a projection operator which is based on applying the if-then clause representation of Boolean functions to multivalued logic circuits, the primitive interval labeled net model is powerful enough to model multivalued logic circuits with timing information and all properties of the interval labeled net. This facilitates a better implementation of the verification and simulation than that using the former net model. The number of token types is reduced from four to two. This model involves simpler types of net adjacency relations. The power of the approach is demonstrated by a logic circuit implemented using logic gates with different rise and fall times. | en_US |
dc.language | eng | en_US |
dc.relation.ispartof | Proceedings - IEEE International Symposium on Circuits and Systems | en_US |
dc.title | Primitive interval labelled net model and timing modelling of logic circuits | en_US |
dc.type | Conference_Paper | en_US |
dc.identifier.email | Cheung, YS:paul.cheung@hku.hk | en_US |
dc.identifier.authority | Cheung, YS=rp00077 | en_US |
dc.description.nature | link_to_subscribed_fulltext | en_US |
dc.identifier.scopus | eid_2-s2.0-0026284653 | en_US |
dc.identifier.volume | 2 | en_US |
dc.identifier.spage | 934 | en_US |
dc.identifier.epage | 937 | en_US |
dc.identifier.scopusauthorid | Chiu, Peter PK=7103182574 | en_US |
dc.identifier.scopusauthorid | Cheung, YS=7202595335 | en_US |
dc.identifier.issnl | 0271-4310 | - |