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Conference Paper: Primitive interval labelled net model and timing modelling of logic circuits

TitlePrimitive interval labelled net model and timing modelling of logic circuits
Authors
Issue Date1991
Citation
Proceedings - Ieee International Symposium On Circuits And Systems, 1991, v. 2, p. 934-937 How to Cite?
AbstractA reduced version of the interval labeled net model called the primitive interval labeled net model is introduced. By incorporating a projection operator which is based on applying the if-then clause representation of Boolean functions to multivalued logic circuits, the primitive interval labeled net model is powerful enough to model multivalued logic circuits with timing information and all properties of the interval labeled net. This facilitates a better implementation of the verification and simulation than that using the former net model. The number of token types is reduced from four to two. This model involves simpler types of net adjacency relations. The power of the approach is demonstrated by a logic circuit implemented using logic gates with different rise and fall times.
Persistent Identifierhttp://hdl.handle.net/10722/158092
ISSN

 

DC FieldValueLanguage
dc.contributor.authorChiu, Peter PKen_US
dc.contributor.authorCheung, YSen_US
dc.date.accessioned2012-08-08T08:58:02Z-
dc.date.available2012-08-08T08:58:02Z-
dc.date.issued1991en_US
dc.identifier.citationProceedings - Ieee International Symposium On Circuits And Systems, 1991, v. 2, p. 934-937en_US
dc.identifier.issn0271-4310en_US
dc.identifier.urihttp://hdl.handle.net/10722/158092-
dc.description.abstractA reduced version of the interval labeled net model called the primitive interval labeled net model is introduced. By incorporating a projection operator which is based on applying the if-then clause representation of Boolean functions to multivalued logic circuits, the primitive interval labeled net model is powerful enough to model multivalued logic circuits with timing information and all properties of the interval labeled net. This facilitates a better implementation of the verification and simulation than that using the former net model. The number of token types is reduced from four to two. This model involves simpler types of net adjacency relations. The power of the approach is demonstrated by a logic circuit implemented using logic gates with different rise and fall times.en_US
dc.languageengen_US
dc.relation.ispartofProceedings - IEEE International Symposium on Circuits and Systemsen_US
dc.titlePrimitive interval labelled net model and timing modelling of logic circuitsen_US
dc.typeConference_Paperen_US
dc.identifier.emailCheung, YS:paul.cheung@hku.hken_US
dc.identifier.authorityCheung, YS=rp00077en_US
dc.description.naturelink_to_subscribed_fulltexten_US
dc.identifier.scopuseid_2-s2.0-0026284653en_US
dc.identifier.volume2en_US
dc.identifier.spage934en_US
dc.identifier.epage937en_US
dc.identifier.scopusauthoridChiu, Peter PK=7103182574en_US
dc.identifier.scopusauthoridCheung, YS=7202595335en_US

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