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Conference Paper: EFFICIENT IMAGE CONVOLUTION USING VLSI.

TitleEFFICIENT IMAGE CONVOLUTION USING VLSI.
Authors
Issue Date1986
Citation
Proceedings - Ieee International Symposium On Circuits And Systems, 1986, p. 1190-1191 How to Cite?
AbstractThe aim of this work is to provide a practical solution to the computation intensive convolution task in image processing which may cope with the amount of low-level processing on high-resolution inputs, and to offer a cost effective number crunching subsystem to industrial image processing systems. The convolution architecture is derived from a recursive methodology which offers extremely high concurrency in the form of hierarchies and the flexibility of either increasing the size and/or the input/output bandwidth of the convolver on chip or off chip. The concurrency of the convolver is the major factor of the speeding-up of the computation, and the flexibility of the architecture makes system implementation and matching much easier. Although the methodology is more for VLSI technology, a TTL prototype system using a 3-by-3 convolver board has been built and is running at 60-ns cycle time for real-time applications on images up to 512 by 512. The concept of the convolution architecture and the VLSI version are discussed.
Persistent Identifierhttp://hdl.handle.net/10722/158002
ISSN

 

DC FieldValueLanguage
dc.contributor.authorSelmane, MKen_US
dc.contributor.authorYung, HCen_US
dc.date.accessioned2012-08-08T08:57:39Z-
dc.date.available2012-08-08T08:57:39Z-
dc.date.issued1986en_US
dc.identifier.citationProceedings - Ieee International Symposium On Circuits And Systems, 1986, p. 1190-1191en_US
dc.identifier.issn0271-4310en_US
dc.identifier.urihttp://hdl.handle.net/10722/158002-
dc.description.abstractThe aim of this work is to provide a practical solution to the computation intensive convolution task in image processing which may cope with the amount of low-level processing on high-resolution inputs, and to offer a cost effective number crunching subsystem to industrial image processing systems. The convolution architecture is derived from a recursive methodology which offers extremely high concurrency in the form of hierarchies and the flexibility of either increasing the size and/or the input/output bandwidth of the convolver on chip or off chip. The concurrency of the convolver is the major factor of the speeding-up of the computation, and the flexibility of the architecture makes system implementation and matching much easier. Although the methodology is more for VLSI technology, a TTL prototype system using a 3-by-3 convolver board has been built and is running at 60-ns cycle time for real-time applications on images up to 512 by 512. The concept of the convolution architecture and the VLSI version are discussed.en_US
dc.languageengen_US
dc.relation.ispartofProceedings - IEEE International Symposium on Circuits and Systemsen_US
dc.titleEFFICIENT IMAGE CONVOLUTION USING VLSI.en_US
dc.typeConference_Paperen_US
dc.identifier.emailYung, HC:nyung@eee.hku.hken_US
dc.identifier.authorityYung, HC=rp00226en_US
dc.description.naturelink_to_subscribed_fulltexten_US
dc.identifier.scopuseid_2-s2.0-0022566622en_US
dc.identifier.spage1190en_US
dc.identifier.epage1191en_US
dc.identifier.scopusauthoridSelmane, MK=6507730646en_US
dc.identifier.scopusauthoridYung, HC=7003473369en_US

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