File Download

There are no files associated with this item.

  Links for fulltext
     (May Require Subscription)
Supplementary

Conference Paper: CONSTRAINED DECOMPOSITION OF BINARY ADDITION FOR VLSI SIGNAL/IMAGE PROCESSING.

TitleCONSTRAINED DECOMPOSITION OF BINARY ADDITION FOR VLSI SIGNAL/IMAGE PROCESSING.
Authors
Issue Date1985
Citation
Proceedings - Ieee International Symposium On Circuits And Systems, 1985, p. 455-458 How to Cite?
AbstractThe constrained decomposition of binary addition is presented for real-time VLSI signal and image processing (SIP), resulting in a high-speed parallel adder design with regular, modular and concurrent architecture with a very local and compact communication network. Its inherent pipelining feature requires straightforward clocking and its recursive structure offers word-size expansion and embedding into a high-level procedural description. The optimality of the addition algorithm is determined by a small (i. e. , 2) global branching ratio greater than 1 and a variable local branching ratio in terms of its cost-performance function. This architectural feature enables a much larger data set and longer word size to be used to design SIP systems with high accuracy and resolution. VLSI implementation and comparison of the algorithm's performance with carry propagate and carry lookahead addition are presented.
Persistent Identifierhttp://hdl.handle.net/10722/158000
ISSN

 

DC FieldValueLanguage
dc.contributor.authorYung, HCen_US
dc.contributor.authorAllen, CRen_US
dc.date.accessioned2012-08-08T08:57:39Z-
dc.date.available2012-08-08T08:57:39Z-
dc.date.issued1985en_US
dc.identifier.citationProceedings - Ieee International Symposium On Circuits And Systems, 1985, p. 455-458en_US
dc.identifier.issn0271-4310en_US
dc.identifier.urihttp://hdl.handle.net/10722/158000-
dc.description.abstractThe constrained decomposition of binary addition is presented for real-time VLSI signal and image processing (SIP), resulting in a high-speed parallel adder design with regular, modular and concurrent architecture with a very local and compact communication network. Its inherent pipelining feature requires straightforward clocking and its recursive structure offers word-size expansion and embedding into a high-level procedural description. The optimality of the addition algorithm is determined by a small (i. e. , 2) global branching ratio greater than 1 and a variable local branching ratio in terms of its cost-performance function. This architectural feature enables a much larger data set and longer word size to be used to design SIP systems with high accuracy and resolution. VLSI implementation and comparison of the algorithm's performance with carry propagate and carry lookahead addition are presented.en_US
dc.languageengen_US
dc.relation.ispartofProceedings - IEEE International Symposium on Circuits and Systemsen_US
dc.titleCONSTRAINED DECOMPOSITION OF BINARY ADDITION FOR VLSI SIGNAL/IMAGE PROCESSING.en_US
dc.typeConference_Paperen_US
dc.identifier.emailYung, HC:nyung@eee.hku.hken_US
dc.identifier.authorityYung, HC=rp00226en_US
dc.description.naturelink_to_subscribed_fulltexten_US
dc.identifier.scopuseid_2-s2.0-0022334872en_US
dc.identifier.spage455en_US
dc.identifier.epage458en_US
dc.identifier.scopusauthoridYung, HC=7003473369en_US
dc.identifier.scopusauthoridAllen, CR=7402266059en_US

Export via OAI-PMH Interface in XML Formats


OR


Export to Other Non-XML Formats