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Article: Reconfigurable FPGA-based switching path frequency-domain echo canceller with applications to voice control device

TitleReconfigurable FPGA-based switching path frequency-domain echo canceller with applications to voice control device
Authors
KeywordsDouble-Talk
Echo Cancellation
Fpga
Speech Recognition
Voice Control
Issue Date2012
PublisherAcademic Press. The Journal's web site is located at http://www.elsevier.com/locate/dsp
Citation
Digital Signal Processing: A Review Journal, 2012, v. 22 n. 2, p. 376-390 How to Cite?
AbstractAcoustic echo control is of vital interest for hands-free operation of telecommunications equipment. An important property of an acoustic echo canceller is its capability to handle double-talk and be able to operate in real time. When it is applied to intelligent voice control device, it is important to suppress the speech from the device and enhance the speech of the user for speech recognition, where double-talk situation is frequently occurred. In this paper, we propose a novel hardware architecture to support a robust adaptive algorithm in combination with a switching path model to tackle the double-talk situation. The proposed switching path model avoids adapting two filters at the same time during double-talk and prevents the disadvantage of the conventional two-path model. In order to achieve computational efficiency and to meet the rigorous timing requirements, the echo canceller is operated in the frequency domain and its computing power is raised by a hardware accelerator implemented in the FPGA fabric surrounding a PowerPC on a Xilinx XUP V2P platform. Results obtained show the echo canceller is successful in handling double-talk situation and the sub-band implementation has improved convergence significantly. An overall improvement by 82.5 times is achieved when a hardware accelerator is used to perform the critical part of the algorithm over a pure software implementation running on a 300 MHz embedded PowerPC processor. © 2011 Elsevier Inc.
Persistent Identifierhttp://hdl.handle.net/10722/155957
ISSN
2015 Impact Factor: 1.444
2015 SCImago Journal Rankings: 0.688
ISI Accession Number ID
Funding AgencyGrant Number
Research Grants Council of HK-SARPolyU 7191/06E
research committee of the Hong Kong Polytechnic University
Funding Information:

This paper is supported by the Research Grants Council of HK-SAR (PolyU 7191/06E) and the research committee of the Hong Kong Polytechnic University.

References

 

DC FieldValueLanguage
dc.contributor.authorYiu, KFCen_US
dc.contributor.authorLu, Yen_US
dc.contributor.authorHok Ho, Cen_US
dc.contributor.authorLuk, Wen_US
dc.contributor.authorHuo, Jen_US
dc.contributor.authorNordholm, Sen_US
dc.date.accessioned2012-08-08T08:38:37Z-
dc.date.available2012-08-08T08:38:37Z-
dc.date.issued2012en_US
dc.identifier.citationDigital Signal Processing: A Review Journal, 2012, v. 22 n. 2, p. 376-390en_US
dc.identifier.issn1051-2004en_US
dc.identifier.urihttp://hdl.handle.net/10722/155957-
dc.description.abstractAcoustic echo control is of vital interest for hands-free operation of telecommunications equipment. An important property of an acoustic echo canceller is its capability to handle double-talk and be able to operate in real time. When it is applied to intelligent voice control device, it is important to suppress the speech from the device and enhance the speech of the user for speech recognition, where double-talk situation is frequently occurred. In this paper, we propose a novel hardware architecture to support a robust adaptive algorithm in combination with a switching path model to tackle the double-talk situation. The proposed switching path model avoids adapting two filters at the same time during double-talk and prevents the disadvantage of the conventional two-path model. In order to achieve computational efficiency and to meet the rigorous timing requirements, the echo canceller is operated in the frequency domain and its computing power is raised by a hardware accelerator implemented in the FPGA fabric surrounding a PowerPC on a Xilinx XUP V2P platform. Results obtained show the echo canceller is successful in handling double-talk situation and the sub-band implementation has improved convergence significantly. An overall improvement by 82.5 times is achieved when a hardware accelerator is used to perform the critical part of the algorithm over a pure software implementation running on a 300 MHz embedded PowerPC processor. © 2011 Elsevier Inc.en_US
dc.languageengen_US
dc.publisherAcademic Press. The Journal's web site is located at http://www.elsevier.com/locate/dspen_US
dc.relation.ispartofDigital Signal Processing: A Review Journalen_US
dc.subjectDouble-Talken_US
dc.subjectEcho Cancellationen_US
dc.subjectFpgaen_US
dc.subjectSpeech Recognitionen_US
dc.subjectVoice Controlen_US
dc.titleReconfigurable FPGA-based switching path frequency-domain echo canceller with applications to voice control deviceen_US
dc.typeArticleen_US
dc.identifier.emailYiu, KFC:cedric@hkucc.hku.hken_US
dc.identifier.authorityYiu, KFC=rp00206en_US
dc.description.naturelink_to_subscribed_fulltexten_US
dc.identifier.doi10.1016/j.dsp.2011.10.008en_US
dc.identifier.scopuseid_2-s2.0-84858080493en_US
dc.relation.referenceshttp://www.scopus.com/mlt/select.url?eid=2-s2.0-84858080493&selection=ref&src=s&origin=recordpageen_US
dc.identifier.volume22en_US
dc.identifier.issue2en_US
dc.identifier.spage376en_US
dc.identifier.epage390en_US
dc.identifier.isiWOS:000302190600021-
dc.publisher.placeUnited Statesen_US
dc.identifier.scopusauthoridYiu, KFC=24802813000en_US
dc.identifier.scopusauthoridLu, Y=54391287900en_US
dc.identifier.scopusauthoridHok Ho, C=54390925600en_US
dc.identifier.scopusauthoridLuk, W=26029526200en_US
dc.identifier.scopusauthoridHuo, J=7006240248en_US
dc.identifier.scopusauthoridNordholm, S=7005690573en_US
dc.identifier.citeulike9998808-

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