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Article: Performance of nonvolatile memory by using band-engineered SrTiO 3/HfON stack as charge-trapping layer

TitlePerformance of nonvolatile memory by using band-engineered SrTiO 3/HfON stack as charge-trapping layer
Authors
Issue Date2012
PublisherPergamon. The Journal's web site is located at http://www.elsevier.com/locate/microrel
Citation
Microelectronics Reliability, 2012, v. 52 n. 11, p. 2527-2531 How to Cite?
AbstractThe charge-trapping properties of band-engineered SrTiO 3/HfON stack were investigated by using the Al/Al 2O 3/SrTiO 3-HfON/SiO 2/Si structure. By adding the HfON layer, the undesirable silicate interlayer due to the reaction of SrTiO 3 with SiO 2 was suppressed as confirmed by X-ray photoelectron spectroscopy, transmission electron microscopy and secondary ion mass spectroscopy. Large memory window (10.6 V at ±12-V sweeping voltage) and high program speed (3.2 V at +12 V for 100 μs) are obtained for this proposed device. Moreover, it exhibits better retention property than another device without the HfON layer (charge loss of 20.0% versus 48.8%) due to suppressed charge-leakage path resulting from the good HfON/SiO 2 interface and band-engineered charge-trapping structure consisting of SrTiO 3 and HfON. © 2012 Elsevier Ltd. All rights reserved.
Persistent Identifierhttp://hdl.handle.net/10722/155757
ISSN
2015 Impact Factor: 1.202
2015 SCImago Journal Rankings: 0.675

 

DC FieldValueLanguage
dc.contributor.authorHuang, XDen_US
dc.contributor.authorLai, PTen_US
dc.contributor.authorSin, JKOen_US
dc.date.accessioned2012-08-08T08:35:12Z-
dc.date.available2012-08-08T08:35:12Z-
dc.date.issued2012en_US
dc.identifier.citationMicroelectronics Reliability, 2012, v. 52 n. 11, p. 2527-2531en_US
dc.identifier.issn0026-2714en_US
dc.identifier.urihttp://hdl.handle.net/10722/155757-
dc.description.abstractThe charge-trapping properties of band-engineered SrTiO 3/HfON stack were investigated by using the Al/Al 2O 3/SrTiO 3-HfON/SiO 2/Si structure. By adding the HfON layer, the undesirable silicate interlayer due to the reaction of SrTiO 3 with SiO 2 was suppressed as confirmed by X-ray photoelectron spectroscopy, transmission electron microscopy and secondary ion mass spectroscopy. Large memory window (10.6 V at ±12-V sweeping voltage) and high program speed (3.2 V at +12 V for 100 μs) are obtained for this proposed device. Moreover, it exhibits better retention property than another device without the HfON layer (charge loss of 20.0% versus 48.8%) due to suppressed charge-leakage path resulting from the good HfON/SiO 2 interface and band-engineered charge-trapping structure consisting of SrTiO 3 and HfON. © 2012 Elsevier Ltd. All rights reserved.en_US
dc.languageengen_US
dc.publisherPergamon. The Journal's web site is located at http://www.elsevier.com/locate/microrelen_US
dc.relation.ispartofMicroelectronics Reliabilityen_US
dc.titlePerformance of nonvolatile memory by using band-engineered SrTiO 3/HfON stack as charge-trapping layeren_US
dc.typeArticleen_US
dc.identifier.emailLai, PT:laip@eee.hku.hken_US
dc.identifier.authorityLai, PT=rp00130en_US
dc.description.naturelink_to_subscribed_fulltexten_US
dc.identifier.doi10.1016/j.microrel.2012.04.006en_US
dc.identifier.scopuseid_2-s2.0-84867571811en_US
dc.identifier.hkuros225947-
dc.publisher.placeUnited Kingdomen_US
dc.identifier.scopusauthoridHuang, XD=55217786600en_US
dc.identifier.scopusauthoridLai, PT=7202946460en_US
dc.identifier.scopusauthoridSin, JKO=7103312667en_US
dc.identifier.citeulike11815066-

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