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Article: Load-balanced three-stage switch
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TitleLoad-balanced three-stage switch
 
AuthorsHu, B2
Yeung, KL1
Zhang, Z2
 
KeywordsLoad-Balanced Switch
Ring Fairness
Three-Stage Switch
Two-Stage Switch
 
Issue Date2012
 
PublisherAcademic Press. The Journal's web site is located at http://www.elsevier.com/locate/jnca
 
CitationJournal Of Network And Computer Applications, 2012, v. 35 n. 1, p. 502-509 [How to Cite?]
DOI: http://dx.doi.org/10.1016/j.jnca.2011.10.011
 
AbstractA load-balanced two-stage switch is scalable and can provide close to 100% throughput. Its major problem is that packets can be mis-sequenced when they arrive at outputs. In a recent work, the packet mis-sequencing problem is elegantly solved by a feedback-based switch architecture. In this paper, we extend the feedback-based switch from two-stage to three-stage for further cutting down average packet delay while still ensuring in-order packet delivery and close to 100% throughput. The basic idea is to use the third stage switch to map heavy flows to experience less middle-stage delays. To identity heavy flows, an adaptive traffic estimation algorithm is proposed. To ensure maxmin fairness in bandwidth allocation under any inadmissible traffic pattern, an efficient fair scheduler is devised. © 2011 Elsevier Ltd. All rights reserved.
 
ISSN1084-8045
2013 Impact Factor: 1.772
 
DOIhttp://dx.doi.org/10.1016/j.jnca.2011.10.011
 
ISI Accession Number IDWOS:000298338600042
Funding AgencyGrant Number
Zhejiang Provincial Natural Science Foundation of ChinaY1100388
Zhejiang Provincial Public Technology Research of China2010C31071
Fundamental Research Funds for the Central Universities2010QNA5032
National Science and Technology Major Project2011ZX03003-003-03
Funding Information:

This work was supported in part by Zhejiang Provincial Natural Science Foundation of China (No. Y1100388), Zhejiang Provincial Public Technology Research of China (No. 2010C31071), Fundamental Research Funds for the Central Universities (No. 2010QNA5032), National Science and Technology Major Project (No. 2011ZX03003-003-03).

 
ReferencesReferences in Scopus
 
DC FieldValue
dc.contributor.authorHu, B
 
dc.contributor.authorYeung, KL
 
dc.contributor.authorZhang, Z
 
dc.date.accessioned2012-08-08T08:34:53Z
 
dc.date.available2012-08-08T08:34:53Z
 
dc.date.issued2012
 
dc.description.abstractA load-balanced two-stage switch is scalable and can provide close to 100% throughput. Its major problem is that packets can be mis-sequenced when they arrive at outputs. In a recent work, the packet mis-sequencing problem is elegantly solved by a feedback-based switch architecture. In this paper, we extend the feedback-based switch from two-stage to three-stage for further cutting down average packet delay while still ensuring in-order packet delivery and close to 100% throughput. The basic idea is to use the third stage switch to map heavy flows to experience less middle-stage delays. To identity heavy flows, an adaptive traffic estimation algorithm is proposed. To ensure maxmin fairness in bandwidth allocation under any inadmissible traffic pattern, an efficient fair scheduler is devised. © 2011 Elsevier Ltd. All rights reserved.
 
dc.description.natureLink_to_subscribed_fulltext
 
dc.identifier.citationJournal Of Network And Computer Applications, 2012, v. 35 n. 1, p. 502-509 [How to Cite?]
DOI: http://dx.doi.org/10.1016/j.jnca.2011.10.011
 
dc.identifier.doihttp://dx.doi.org/10.1016/j.jnca.2011.10.011
 
dc.identifier.epage509
 
dc.identifier.isiWOS:000298338600042
Funding AgencyGrant Number
Zhejiang Provincial Natural Science Foundation of ChinaY1100388
Zhejiang Provincial Public Technology Research of China2010C31071
Fundamental Research Funds for the Central Universities2010QNA5032
National Science and Technology Major Project2011ZX03003-003-03
Funding Information:

This work was supported in part by Zhejiang Provincial Natural Science Foundation of China (No. Y1100388), Zhejiang Provincial Public Technology Research of China (No. 2010C31071), Fundamental Research Funds for the Central Universities (No. 2010QNA5032), National Science and Technology Major Project (No. 2011ZX03003-003-03).

 
dc.identifier.issn1084-8045
2013 Impact Factor: 1.772
 
dc.identifier.issue1
 
dc.identifier.scopuseid_2-s2.0-82155166277
 
dc.identifier.spage502
 
dc.identifier.urihttp://hdl.handle.net/10722/155702
 
dc.identifier.volume35
 
dc.languageeng
 
dc.publisherAcademic Press. The Journal's web site is located at http://www.elsevier.com/locate/jnca
 
dc.publisher.placeUnited Kingdom
 
dc.relation.ispartofJournal of Network and Computer Applications
 
dc.relation.referencesReferences in Scopus
 
dc.subjectLoad-Balanced Switch
 
dc.subjectRing Fairness
 
dc.subjectThree-Stage Switch
 
dc.subjectTwo-Stage Switch
 
dc.titleLoad-balanced three-stage switch
 
dc.typeArticle
 
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Author Affiliations
  1. The University of Hong Kong
  2. Zhejiang University