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Article: Load-balanced three-stage switch

TitleLoad-balanced three-stage switch
Authors
KeywordsLoad-Balanced Switch
Ring Fairness
Three-Stage Switch
Two-Stage Switch
Issue Date2012
PublisherAcademic Press. The Journal's web site is located at http://www.elsevier.com/locate/jnca
Citation
Journal Of Network And Computer Applications, 2012, v. 35 n. 1, p. 502-509 How to Cite?
Abstract
A load-balanced two-stage switch is scalable and can provide close to 100% throughput. Its major problem is that packets can be mis-sequenced when they arrive at outputs. In a recent work, the packet mis-sequencing problem is elegantly solved by a feedback-based switch architecture. In this paper, we extend the feedback-based switch from two-stage to three-stage for further cutting down average packet delay while still ensuring in-order packet delivery and close to 100% throughput. The basic idea is to use the third stage switch to map heavy flows to experience less middle-stage delays. To identity heavy flows, an adaptive traffic estimation algorithm is proposed. To ensure maxmin fairness in bandwidth allocation under any inadmissible traffic pattern, an efficient fair scheduler is devised. © 2011 Elsevier Ltd. All rights reserved.
Persistent Identifierhttp://hdl.handle.net/10722/155702
ISSN
2013 Impact Factor: 1.772
ISI Accession Number ID
Funding AgencyGrant Number
Zhejiang Provincial Natural Science Foundation of ChinaY1100388
Zhejiang Provincial Public Technology Research of China2010C31071
Fundamental Research Funds for the Central Universities2010QNA5032
National Science and Technology Major Project2011ZX03003-003-03
Funding Information:

This work was supported in part by Zhejiang Provincial Natural Science Foundation of China (No. Y1100388), Zhejiang Provincial Public Technology Research of China (No. 2010C31071), Fundamental Research Funds for the Central Universities (No. 2010QNA5032), National Science and Technology Major Project (No. 2011ZX03003-003-03).

References

 

DC FieldValueLanguage
dc.contributor.authorHu, Ben_US
dc.contributor.authorYeung, KLen_US
dc.contributor.authorZhang, Zen_US
dc.date.accessioned2012-08-08T08:34:53Z-
dc.date.available2012-08-08T08:34:53Z-
dc.date.issued2012en_US
dc.identifier.citationJournal Of Network And Computer Applications, 2012, v. 35 n. 1, p. 502-509en_US
dc.identifier.issn1084-8045en_US
dc.identifier.urihttp://hdl.handle.net/10722/155702-
dc.description.abstractA load-balanced two-stage switch is scalable and can provide close to 100% throughput. Its major problem is that packets can be mis-sequenced when they arrive at outputs. In a recent work, the packet mis-sequencing problem is elegantly solved by a feedback-based switch architecture. In this paper, we extend the feedback-based switch from two-stage to three-stage for further cutting down average packet delay while still ensuring in-order packet delivery and close to 100% throughput. The basic idea is to use the third stage switch to map heavy flows to experience less middle-stage delays. To identity heavy flows, an adaptive traffic estimation algorithm is proposed. To ensure maxmin fairness in bandwidth allocation under any inadmissible traffic pattern, an efficient fair scheduler is devised. © 2011 Elsevier Ltd. All rights reserved.en_US
dc.languageengen_US
dc.publisherAcademic Press. The Journal's web site is located at http://www.elsevier.com/locate/jncaen_US
dc.relation.ispartofJournal of Network and Computer Applicationsen_US
dc.subjectLoad-Balanced Switchen_US
dc.subjectRing Fairnessen_US
dc.subjectThree-Stage Switchen_US
dc.subjectTwo-Stage Switchen_US
dc.titleLoad-balanced three-stage switchen_US
dc.typeArticleen_US
dc.identifier.emailYeung, KL:kyeung@eee.hku.hken_US
dc.identifier.authorityYeung, KL=rp00204en_US
dc.description.naturelink_to_subscribed_fulltexten_US
dc.identifier.doi10.1016/j.jnca.2011.10.011en_US
dc.identifier.scopuseid_2-s2.0-82155166277en_US
dc.relation.referenceshttp://www.scopus.com/mlt/select.url?eid=2-s2.0-82155166277&selection=ref&src=s&origin=recordpageen_US
dc.identifier.volume35en_US
dc.identifier.issue1en_US
dc.identifier.spage502en_US
dc.identifier.epage509en_US
dc.identifier.isiWOS:000298338600042-
dc.publisher.placeUnited Kingdomen_US
dc.identifier.scopusauthoridHu, B=36617158500en_US
dc.identifier.scopusauthoridYeung, KL=7202424908en_US
dc.identifier.scopusauthoridZhang, Z=35263460700en_US

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