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Article: Fluorinated SrTiO3 as charge-trapping layer for nonvolatile memory applications

TitleFluorinated SrTiO3 as charge-trapping layer for nonvolatile memory applications
Authors
Huang, XDSin, JKOLai, PT
KeywordsCharge-Trapping (Ct) Layer (Ctl)
Fluorine Treatment
High-K
Nonvolatile Memory
Srtio 3
Issue Date2011
PublisherIEEE. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=16
Citation
IEEE Transactions on Electron Devices, 2011, v. 58 n. 12, p. 4235-4240 How to Cite?
DOI: http://dx.doi.org/10.1109/TED.2011.2169675
AbstractCharge-trapping properties of SrTiO 3 with and without fluorine incorporation are investigated by using an Al/Al 2O 3/SrTiO 3/SiO 2/Si structure. The memory device with a fluorinated SrTiO 3 film shows promising performance in terms of large memory window (8.8 V) by ± 8-V sweeping voltage, large flatband-voltage (V FB) shift (2.5 V) at a low gate voltage of +6 V for 1 ms, negligible V FB shift after 10 5-cycle program/erase stressing, and improved data retention compared with that without fluorine treatment. These advantages can be associated with generated deep-level traps, reduced leakage path, and enhanced strength of the film due to the fluorine incorporation. © 2011 IEEE.
Persistent Identifierhttp://hdl.handle.net/10722/155700
ISSN
0018-9383
2023 Impact Factor: 2.9
2023 SCImago Journal Rankings: 0.785
ISI Accession Number ID
WOS:000297337000014
References
References in Scopus

 

DC FieldValueLanguage
dc.contributor.authorHuang, XDen_US
dc.contributor.authorSin, JKOen_US
dc.contributor.authorLai, PTen_US
dc.date.accessioned2012-08-08T08:34:53Z-
dc.date.available2012-08-08T08:34:53Z-
dc.date.issued2011en_US
dc.identifier.citationIEEE Transactions on Electron Devices, 2011, v. 58 n. 12, p. 4235-4240en_US
dc.identifier.issn0018-9383en_US
dc.identifier.urihttp://hdl.handle.net/10722/155700-
dc.description.abstractCharge-trapping properties of SrTiO 3 with and without fluorine incorporation are investigated by using an Al/Al 2O 3/SrTiO 3/SiO 2/Si structure. The memory device with a fluorinated SrTiO 3 film shows promising performance in terms of large memory window (8.8 V) by ± 8-V sweeping voltage, large flatband-voltage (V FB) shift (2.5 V) at a low gate voltage of +6 V for 1 ms, negligible V FB shift after 10 5-cycle program/erase stressing, and improved data retention compared with that without fluorine treatment. These advantages can be associated with generated deep-level traps, reduced leakage path, and enhanced strength of the film due to the fluorine incorporation. © 2011 IEEE.en_US
dc.languageengen_US
dc.publisherIEEE. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=16en_US
dc.relation.ispartofIEEE Transactions on Electron Devicesen_US
dc.subjectCharge-Trapping (Ct) Layer (Ctl)en_US
dc.subjectFluorine Treatmenten_US
dc.subjectHigh-Ken_US
dc.subjectNonvolatile Memoryen_US
dc.subjectSrtio 3en_US
dc.titleFluorinated SrTiO3 as charge-trapping layer for nonvolatile memory applicationsen_US
dc.typeArticleen_US
dc.identifier.emailLai, PT:laip@eee.hku.hken_US
dc.identifier.authorityLai, PT=rp00130en_US
dc.description.naturelink_to_subscribed_fulltexten_US
dc.identifier.doi10.1109/TED.2011.2169675en_US
dc.identifier.scopuseid_2-s2.0-82155162321en_US
dc.identifier.hkuros225734-
dc.relation.referenceshttp://www.scopus.com/mlt/select.url?eid=2-s2.0-82155162321&selection=ref&src=s&origin=recordpageen_US
dc.identifier.volume58en_US
dc.identifier.issue12en_US
dc.identifier.spage4235en_US
dc.identifier.epage4240en_US
dc.identifier.isiWOS:000297337000014-
dc.publisher.placeUnited Statesen_US
dc.identifier.scopusauthoridHuang, XD=37057428400en_US
dc.identifier.scopusauthoridSin, JKO=7103312667en_US
dc.identifier.scopusauthoridLai, PT=7202946460en_US
dc.identifier.issnl0018-9383-

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