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Article: Design space exploration for sparse matrix-matrix multiplication on FPGAs
Title | Design space exploration for sparse matrix-matrix multiplication on FPGAs |
---|---|
Authors | |
Keywords | Design Space Exploration Field-Programmable Gate Array Sparse Sparse Matrix-Matrix Multiplication |
Issue Date | 2013 |
Publisher | John Wiley & Sons Ltd. The Journal's web site is located at http://www3.interscience.wiley.com/cgi-bin/jhome/1976 |
Citation | International Journal Of Circuit Theory And Applications, 2013, v. 41 n. 2, p. 205-219 How to Cite? |
Abstract | The design and implementation of a sparse matrix-matrix multiplication architecture on field-programmable gate arrays is presented. Performance of the design, in terms of computational latency, as well as the associated power-delay and energy-delay tradeoff are studied. Taking advantage of the sparsity of the input matrices, the proposed design allows user-tunable power-delay and energy-delay tradeoffs by employing different number of processing elements (PEs) in the architecture design and different block size in the blocking decomposition. Such ability allows designers to employ different on-chip computational architecture for different system power-delay and energy-delay requirements. It is in contrast to conventional dense matrix-matrix multiplication architectures that always favor the maximum number of PEs and largest block size. In our implementation, the better energy consumption and power-delay product favors less PEs and smaller block size for the 90%-sparsity matrix-matrix multiplications. Although in order to achieve better energy-delay product, more PEs and larger block size are preferred. © 2011 John Wiley & Sons, Ltd.. |
Persistent Identifier | http://hdl.handle.net/10722/155673 |
ISSN | 2023 Impact Factor: 1.8 2023 SCImago Journal Rankings: 0.380 |
ISI Accession Number ID |
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lin, CY | en_US |
dc.contributor.author | Wong, N | en_US |
dc.contributor.author | So, HKH | en_US |
dc.date.accessioned | 2012-08-08T08:34:46Z | - |
dc.date.available | 2012-08-08T08:34:46Z | - |
dc.date.issued | 2013 | en_US |
dc.identifier.citation | International Journal Of Circuit Theory And Applications, 2013, v. 41 n. 2, p. 205-219 | en_US |
dc.identifier.issn | 0098-9886 | en_US |
dc.identifier.uri | http://hdl.handle.net/10722/155673 | - |
dc.description.abstract | The design and implementation of a sparse matrix-matrix multiplication architecture on field-programmable gate arrays is presented. Performance of the design, in terms of computational latency, as well as the associated power-delay and energy-delay tradeoff are studied. Taking advantage of the sparsity of the input matrices, the proposed design allows user-tunable power-delay and energy-delay tradeoffs by employing different number of processing elements (PEs) in the architecture design and different block size in the blocking decomposition. Such ability allows designers to employ different on-chip computational architecture for different system power-delay and energy-delay requirements. It is in contrast to conventional dense matrix-matrix multiplication architectures that always favor the maximum number of PEs and largest block size. In our implementation, the better energy consumption and power-delay product favors less PEs and smaller block size for the 90%-sparsity matrix-matrix multiplications. Although in order to achieve better energy-delay product, more PEs and larger block size are preferred. © 2011 John Wiley & Sons, Ltd.. | en_US |
dc.language | eng | en_US |
dc.publisher | John Wiley & Sons Ltd. The Journal's web site is located at http://www3.interscience.wiley.com/cgi-bin/jhome/1976 | en_US |
dc.relation.ispartof | International Journal of Circuit Theory and Applications | en_US |
dc.subject | Design Space Exploration | en_US |
dc.subject | Field-Programmable Gate Array | en_US |
dc.subject | Sparse | en_US |
dc.subject | Sparse Matrix-Matrix Multiplication | en_US |
dc.title | Design space exploration for sparse matrix-matrix multiplication on FPGAs | en_US |
dc.type | Article | en_US |
dc.identifier.email | Wong, N:nwong@eee.hku.hk | en_US |
dc.identifier.email | So, HKH:hso@eee.hku.hk | en_US |
dc.identifier.authority | Wong, N=rp00190 | en_US |
dc.identifier.authority | So, HKH=rp00169 | en_US |
dc.description.nature | link_to_subscribed_fulltext | en_US |
dc.identifier.doi | 10.1002/cta.796 | en_US |
dc.identifier.scopus | eid_2-s2.0-84873709022 | en_US |
dc.identifier.hkuros | 217516 | - |
dc.identifier.isi | WOS:000314935500006 | - |
dc.publisher.place | United Kingdom | en_US |
dc.identifier.scopusauthorid | Lin, CY=35177986900 | en_US |
dc.identifier.scopusauthorid | Wong, N=35235551600 | en_US |
dc.identifier.scopusauthorid | So, HKH=10738896800 | en_US |
dc.identifier.issnl | 0098-9886 | - |