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Article: Design space exploration for sparse matrix-matrix multiplication on FPGAs

TitleDesign space exploration for sparse matrix-matrix multiplication on FPGAs
Authors
KeywordsDesign Space Exploration
Field-Programmable Gate Array
Sparse
Sparse Matrix-Matrix Multiplication
Issue Date2013
PublisherJohn Wiley & Sons Ltd. The Journal's web site is located at http://www3.interscience.wiley.com/cgi-bin/jhome/1976
Citation
International Journal Of Circuit Theory And Applications, 2013, v. 41 n. 2, p. 205-219 How to Cite?
AbstractThe design and implementation of a sparse matrix-matrix multiplication architecture on field-programmable gate arrays is presented. Performance of the design, in terms of computational latency, as well as the associated power-delay and energy-delay tradeoff are studied. Taking advantage of the sparsity of the input matrices, the proposed design allows user-tunable power-delay and energy-delay tradeoffs by employing different number of processing elements (PEs) in the architecture design and different block size in the blocking decomposition. Such ability allows designers to employ different on-chip computational architecture for different system power-delay and energy-delay requirements. It is in contrast to conventional dense matrix-matrix multiplication architectures that always favor the maximum number of PEs and largest block size. In our implementation, the better energy consumption and power-delay product favors less PEs and smaller block size for the 90%-sparsity matrix-matrix multiplications. Although in order to achieve better energy-delay product, more PEs and larger block size are preferred. © 2011 John Wiley & Sons, Ltd..
Persistent Identifierhttp://hdl.handle.net/10722/155673
ISSN
2015 Impact Factor: 1.179
2015 SCImago Journal Rankings: 0.384
ISI Accession Number ID

 

DC FieldValueLanguage
dc.contributor.authorLin, CYen_US
dc.contributor.authorWong, Nen_US
dc.contributor.authorSo, HKHen_US
dc.date.accessioned2012-08-08T08:34:46Z-
dc.date.available2012-08-08T08:34:46Z-
dc.date.issued2013en_US
dc.identifier.citationInternational Journal Of Circuit Theory And Applications, 2013, v. 41 n. 2, p. 205-219en_US
dc.identifier.issn0098-9886en_US
dc.identifier.urihttp://hdl.handle.net/10722/155673-
dc.description.abstractThe design and implementation of a sparse matrix-matrix multiplication architecture on field-programmable gate arrays is presented. Performance of the design, in terms of computational latency, as well as the associated power-delay and energy-delay tradeoff are studied. Taking advantage of the sparsity of the input matrices, the proposed design allows user-tunable power-delay and energy-delay tradeoffs by employing different number of processing elements (PEs) in the architecture design and different block size in the blocking decomposition. Such ability allows designers to employ different on-chip computational architecture for different system power-delay and energy-delay requirements. It is in contrast to conventional dense matrix-matrix multiplication architectures that always favor the maximum number of PEs and largest block size. In our implementation, the better energy consumption and power-delay product favors less PEs and smaller block size for the 90%-sparsity matrix-matrix multiplications. Although in order to achieve better energy-delay product, more PEs and larger block size are preferred. © 2011 John Wiley & Sons, Ltd..en_US
dc.languageengen_US
dc.publisherJohn Wiley & Sons Ltd. The Journal's web site is located at http://www3.interscience.wiley.com/cgi-bin/jhome/1976en_US
dc.relation.ispartofInternational Journal of Circuit Theory and Applicationsen_US
dc.subjectDesign Space Explorationen_US
dc.subjectField-Programmable Gate Arrayen_US
dc.subjectSparseen_US
dc.subjectSparse Matrix-Matrix Multiplicationen_US
dc.titleDesign space exploration for sparse matrix-matrix multiplication on FPGAsen_US
dc.typeArticleen_US
dc.identifier.emailWong, N:nwong@eee.hku.hken_US
dc.identifier.emailSo, HKH:hso@eee.hku.hken_US
dc.identifier.authorityWong, N=rp00190en_US
dc.identifier.authoritySo, HKH=rp00169en_US
dc.description.naturelink_to_subscribed_fulltexten_US
dc.identifier.doi10.1002/cta.796en_US
dc.identifier.scopuseid_2-s2.0-84873709022en_US
dc.identifier.hkuros217516-
dc.identifier.isiWOS:000314935500006-
dc.publisher.placeUnited Kingdomen_US
dc.identifier.scopusauthoridLin, CY=35177986900en_US
dc.identifier.scopusauthoridWong, N=35235551600en_US
dc.identifier.scopusauthoridSo, HKH=10738896800en_US

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