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Article: Improved interface properties of Ge metal-oxide-semiconductor capacitor with TaTiO gate dielectric by using in situ TaON passivation interlayer
Title | Improved interface properties of Ge metal-oxide-semiconductor capacitor with TaTiO gate dielectric by using in situ TaON passivation interlayer | ||||||||
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Authors | |||||||||
Issue Date | 2011 | ||||||||
Publisher | American Institute of Physics. The Journal's web site is located at http://apl.aip.org/ | ||||||||
Citation | Applied Physics Letters, 2011, v. 98 n. 18, article no. 182901 How to Cite? | ||||||||
Abstract | TaON is in situ formed as a passivating interlayer in Ge metal-oxide-semiconductor (MOS) capacitors with high-k TaTiO gate dielectric fabricated simply by alternate sputtering of Ta and Ti. Also, postdeposition annealing is performed in wet N 2 to suppress the growth of unstable GeO x at the Ge surface. As a result, excellent electrical properties of the Ge MOS devices are demonstrated, such as high equivalent dielectric constant (22.1), low interface-state density (7.3× 10 11 cm -2 eV), small gate leakage current (8.6× 10 -4 A cm -2 at V g -V fb =1 V), and high device reliability. Transmission electron microscopy and x-ray photoelectron spectroscopy support that all these should be attributed to the fact that the nitrogen barrier in the TaON interlayer can effectively block the interdiffusions of Ge and Ta, and the wet- N 2 anneal can significantly suppress the growth of unstable low-k GeO x. © 2011 American Institute of Physics. | ||||||||
Persistent Identifier | http://hdl.handle.net/10722/155613 | ||||||||
ISSN | 2023 Impact Factor: 3.5 2023 SCImago Journal Rankings: 0.976 | ||||||||
ISI Accession Number ID |
Funding Information: This work is financially supported by the National Natural Science Foundation of China (Grant No. 60776016), the Postdoctoral Science Foundation of China (Grant No. 20100470056), the RGC of HKSAR, China (Project No. HKU 713308E). | ||||||||
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DC Field | Value | Language |
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dc.contributor.author | Ji, F | en_US |
dc.contributor.author | Xu, JP | en_US |
dc.contributor.author | Liu, JG | en_US |
dc.contributor.author | Li, CX | en_US |
dc.contributor.author | Lai, PT | en_US |
dc.date.accessioned | 2012-08-08T08:34:22Z | - |
dc.date.available | 2012-08-08T08:34:22Z | - |
dc.date.issued | 2011 | en_US |
dc.identifier.citation | Applied Physics Letters, 2011, v. 98 n. 18, article no. 182901 | - |
dc.identifier.issn | 0003-6951 | en_US |
dc.identifier.uri | http://hdl.handle.net/10722/155613 | - |
dc.description.abstract | TaON is in situ formed as a passivating interlayer in Ge metal-oxide-semiconductor (MOS) capacitors with high-k TaTiO gate dielectric fabricated simply by alternate sputtering of Ta and Ti. Also, postdeposition annealing is performed in wet N 2 to suppress the growth of unstable GeO x at the Ge surface. As a result, excellent electrical properties of the Ge MOS devices are demonstrated, such as high equivalent dielectric constant (22.1), low interface-state density (7.3× 10 11 cm -2 eV), small gate leakage current (8.6× 10 -4 A cm -2 at V g -V fb =1 V), and high device reliability. Transmission electron microscopy and x-ray photoelectron spectroscopy support that all these should be attributed to the fact that the nitrogen barrier in the TaON interlayer can effectively block the interdiffusions of Ge and Ta, and the wet- N 2 anneal can significantly suppress the growth of unstable low-k GeO x. © 2011 American Institute of Physics. | en_US |
dc.language | eng | en_US |
dc.publisher | American Institute of Physics. The Journal's web site is located at http://apl.aip.org/ | en_US |
dc.relation.ispartof | Applied Physics Letters | en_US |
dc.title | Improved interface properties of Ge metal-oxide-semiconductor capacitor with TaTiO gate dielectric by using in situ TaON passivation interlayer | en_US |
dc.type | Article | en_US |
dc.identifier.email | Lai, PT:laip@eee.hku.hk | en_US |
dc.identifier.authority | Lai, PT=rp00130 | en_US |
dc.description.nature | link_to_subscribed_fulltext | en_US |
dc.identifier.doi | 10.1063/1.3581891 | en_US |
dc.identifier.scopus | eid_2-s2.0-79957466868 | en_US |
dc.relation.references | http://www.scopus.com/mlt/select.url?eid=2-s2.0-79957466868&selection=ref&src=s&origin=recordpage | en_US |
dc.identifier.volume | 98 | en_US |
dc.identifier.issue | 18 | en_US |
dc.identifier.spage | article no. 182901 | - |
dc.identifier.epage | article no. 182901 | - |
dc.identifier.isi | WOS:000290392300039 | - |
dc.publisher.place | United States | en_US |
dc.relation.project | High-k Gate Dielectrics for High-Performance Germanium MISFET's | - |
dc.identifier.scopusauthorid | Ji, F=8238553900 | en_US |
dc.identifier.scopusauthorid | Xu, JP=35754128700 | en_US |
dc.identifier.scopusauthorid | Liu, JG=35206342900 | en_US |
dc.identifier.scopusauthorid | Li, CX=13906721600 | en_US |
dc.identifier.scopusauthorid | Lai, PT=7202946460 | en_US |
dc.identifier.issnl | 0003-6951 | - |