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Article: Improved interfacial properties of Ge MOS capacitor with high-k dielectric by using TaON/GeON dual interlayer
Title | Improved interfacial properties of Ge MOS capacitor with high-k dielectric by using TaON/GeON dual interlayer | ||||||||||||
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Authors | |||||||||||||
Keywords | Ge Mos High K Taon/Geon Terms-Dual Interlayer | ||||||||||||
Issue Date | 2011 | ||||||||||||
Publisher | I E E E. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=55 | ||||||||||||
Citation | Ieee Electron Device Letters, 2011, v. 32 n. 2, p. 122-124 How to Cite? | ||||||||||||
Abstract | Ge MOS capacitors with tri-layer gate dielectric are proposed by using GeON interlayer, TaON sandwich layer, and HfTiON high-k dielectric. Very small capacitance equivalent thickness (0.79 ∼ 0.91 nm) is achieved. Experimental results show that the NO pretreated sample exhibits the best electrical properties, such as low interface-state density (5.4 × 10 11 cm -2eV.1), low gate leakage current density (∼3.16 × 10 -4 Acm -2 at Vg . Vfb = 1 V) and high device reliability. All of these should be attributed to the facts that the NO nitridation could form a GeON interlayer with suitable N content and thus provide an excellent GeON/Ge interface with strong Ge-N bonds, while the TaON sandwich layer could separate Hf and Ge, thus effectively preventing the reaction between them and improving the interface quality and electrical properties of the devices. © 2010 IEEE. | ||||||||||||
Persistent Identifier | http://hdl.handle.net/10722/155601 | ||||||||||||
ISSN | 2023 Impact Factor: 4.1 2023 SCImago Journal Rankings: 1.250 | ||||||||||||
ISI Accession Number ID |
Funding Information: This work was supported by the National Natural Science Foundation of China under Grant 60776016, the Postdoctoral Foundation of China under Grant 20100470056, the RGC of HKSAR, China (Project no. HKU 713308E), the Small Project Funding of the University of Hong Kong (Project 200707176147), and the University Development Fund (Nanotechnology Research Institute, 00600009) of the University of Hong Kong. The review of this letter was arranged by Editor M. Passlack. | ||||||||||||
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DC Field | Value | Language |
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dc.contributor.author | Ji, F | en_US |
dc.contributor.author | Xu, JP | en_US |
dc.contributor.author | Lai, PT | en_US |
dc.contributor.author | Li, CX | en_US |
dc.contributor.author | Liu, JG | en_US |
dc.date.accessioned | 2012-08-08T08:34:18Z | - |
dc.date.available | 2012-08-08T08:34:18Z | - |
dc.date.issued | 2011 | en_US |
dc.identifier.citation | Ieee Electron Device Letters, 2011, v. 32 n. 2, p. 122-124 | en_US |
dc.identifier.issn | 0741-3106 | en_US |
dc.identifier.uri | http://hdl.handle.net/10722/155601 | - |
dc.description.abstract | Ge MOS capacitors with tri-layer gate dielectric are proposed by using GeON interlayer, TaON sandwich layer, and HfTiON high-k dielectric. Very small capacitance equivalent thickness (0.79 ∼ 0.91 nm) is achieved. Experimental results show that the NO pretreated sample exhibits the best electrical properties, such as low interface-state density (5.4 × 10 11 cm -2eV.1), low gate leakage current density (∼3.16 × 10 -4 Acm -2 at Vg . Vfb = 1 V) and high device reliability. All of these should be attributed to the facts that the NO nitridation could form a GeON interlayer with suitable N content and thus provide an excellent GeON/Ge interface with strong Ge-N bonds, while the TaON sandwich layer could separate Hf and Ge, thus effectively preventing the reaction between them and improving the interface quality and electrical properties of the devices. © 2010 IEEE. | en_US |
dc.language | eng | en_US |
dc.publisher | I E E E. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=55 | en_US |
dc.relation.ispartof | IEEE Electron Device Letters | en_US |
dc.subject | Ge Mos | en_US |
dc.subject | High K | en_US |
dc.subject | Taon/Geon | en_US |
dc.subject | Terms-Dual Interlayer | en_US |
dc.title | Improved interfacial properties of Ge MOS capacitor with high-k dielectric by using TaON/GeON dual interlayer | en_US |
dc.type | Article | en_US |
dc.identifier.email | Lai, PT:laip@eee.hku.hk | en_US |
dc.identifier.authority | Lai, PT=rp00130 | en_US |
dc.description.nature | link_to_subscribed_fulltext | en_US |
dc.identifier.doi | 10.1109/LED.2010.2092749 | en_US |
dc.identifier.scopus | eid_2-s2.0-79151480537 | en_US |
dc.relation.references | http://www.scopus.com/mlt/select.url?eid=2-s2.0-79151480537&selection=ref&src=s&origin=recordpage | en_US |
dc.identifier.volume | 32 | en_US |
dc.identifier.issue | 2 | en_US |
dc.identifier.spage | 122 | en_US |
dc.identifier.epage | 124 | en_US |
dc.identifier.isi | WOS:000286677700004 | - |
dc.publisher.place | United States | en_US |
dc.relation.project | High-k Gate Dielectrics for High-Performance Germanium MISFET's | - |
dc.identifier.scopusauthorid | Ji, F=8238553900 | en_US |
dc.identifier.scopusauthorid | Xu, JP=35754128700 | en_US |
dc.identifier.scopusauthorid | Lai, PT=7202946460 | en_US |
dc.identifier.scopusauthorid | Li, CX=13906721600 | en_US |
dc.identifier.scopusauthorid | Liu, JG=35206342900 | en_US |
dc.identifier.issnl | 0741-3106 | - |