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Article: Effects of Ti content and wet-N2 anneal on Ge MOS capacitors with HfTiO gate dielectric

TitleEffects of Ti content and wet-N2 anneal on Ge MOS capacitors with HfTiO gate dielectric
Authors
Issue Date2008
PublisherPergamon. The Journal's web site is located at http://www.elsevier.com/locate/microrel
Citation
Microelectronics Reliability, 2008, v. 48 n. 4, p. 526-530 How to Cite?
AbstractThin HfTiO gate dielectric is deposited by reactive co-sputtering method followed by wet or dry N2 anneal. The effects of Ti content on the performance of HfTiO gate dielectric are investigated by using different sputtering powers for the Ti target. Experimental results indicate that as the Ti content increases, the dielectric constant (κ) can increase up to 40 for a Ti content of 28%. However, when the Ti content is too high, the interface properties and gate leakage properties are deteriorated. On the contrary, results show that owing to the hydrolyzable property of GeOx, the wet-N2 anneal can greatly suppress the growth of unstable low-κ GeOx interlayer, resulting in lower interface-state density and gate leakage current, in addition to larger κ value. In this study, when the sputtering power of the Ti target is 80 W together with a 25-W power for the Hf target and a post-deposition anneal (PDA) in wet-N2 ambient at 500 °C for 300 s, excellent device performance is achieved: equivalent oxide thickness of 0.72 nm, equivalent dielectric constant of 39, interface-state density of 6.5 × 1011 eV-1 cm-2 and gate leakage current of 5.7 × 10-4 A/cm2 at Vg = 1 V. Therefore, in order to obtain high-quality HfTiO gate dielectric for small-scaled Ge MOS devices, not only should the Ti content be optimized, the PDA should also be done in a wet-N2 ambient. © 2007 Elsevier Ltd. All rights reserved.
Persistent Identifierhttp://hdl.handle.net/10722/155456
ISSN
2015 Impact Factor: 1.202
2015 SCImago Journal Rankings: 0.675
ISI Accession Number ID
References

 

DC FieldValueLanguage
dc.contributor.authorLi, CXen_HK
dc.contributor.authorZou, Xen_HK
dc.contributor.authorLai, PTen_HK
dc.contributor.authorXu, JPen_HK
dc.contributor.authorChan, CLen_HK
dc.date.accessioned2012-08-08T08:33:35Z-
dc.date.available2012-08-08T08:33:35Z-
dc.date.issued2008en_HK
dc.identifier.citationMicroelectronics Reliability, 2008, v. 48 n. 4, p. 526-530en_HK
dc.identifier.issn0026-2714en_HK
dc.identifier.urihttp://hdl.handle.net/10722/155456-
dc.description.abstractThin HfTiO gate dielectric is deposited by reactive co-sputtering method followed by wet or dry N2 anneal. The effects of Ti content on the performance of HfTiO gate dielectric are investigated by using different sputtering powers for the Ti target. Experimental results indicate that as the Ti content increases, the dielectric constant (κ) can increase up to 40 for a Ti content of 28%. However, when the Ti content is too high, the interface properties and gate leakage properties are deteriorated. On the contrary, results show that owing to the hydrolyzable property of GeOx, the wet-N2 anneal can greatly suppress the growth of unstable low-κ GeOx interlayer, resulting in lower interface-state density and gate leakage current, in addition to larger κ value. In this study, when the sputtering power of the Ti target is 80 W together with a 25-W power for the Hf target and a post-deposition anneal (PDA) in wet-N2 ambient at 500 °C for 300 s, excellent device performance is achieved: equivalent oxide thickness of 0.72 nm, equivalent dielectric constant of 39, interface-state density of 6.5 × 1011 eV-1 cm-2 and gate leakage current of 5.7 × 10-4 A/cm2 at Vg = 1 V. Therefore, in order to obtain high-quality HfTiO gate dielectric for small-scaled Ge MOS devices, not only should the Ti content be optimized, the PDA should also be done in a wet-N2 ambient. © 2007 Elsevier Ltd. All rights reserved.en_HK
dc.languageengen_US
dc.publisherPergamon. The Journal's web site is located at http://www.elsevier.com/locate/microrelen_HK
dc.relation.ispartofMicroelectronics Reliabilityen_HK
dc.titleEffects of Ti content and wet-N2 anneal on Ge MOS capacitors with HfTiO gate dielectricen_HK
dc.typeArticleen_HK
dc.identifier.emailLai, PT: laip@eee.hku.hken_HK
dc.identifier.emailXu, JP: jpxu@eee.hku.hken_HK
dc.identifier.authorityLai, PT=rp00130en_HK
dc.identifier.authorityXu, JP=rp00197en_HK
dc.description.naturelink_to_subscribed_fulltexten_US
dc.identifier.doi10.1016/j.microrel.2007.11.004en_HK
dc.identifier.scopuseid_2-s2.0-42649115113en_HK
dc.identifier.hkuros150345-
dc.relation.referenceshttp://www.scopus.com/mlt/select.url?eid=2-s2.0-42649115113&selection=ref&src=s&origin=recordpageen_HK
dc.identifier.volume48en_HK
dc.identifier.issue4en_HK
dc.identifier.spage526en_HK
dc.identifier.epage530en_HK
dc.identifier.isiWOS:000256454300005-
dc.publisher.placeUnited Kingdomen_HK
dc.identifier.scopusauthoridLi, CX=22034888200en_HK
dc.identifier.scopusauthoridZou, X=23020170400en_HK
dc.identifier.scopusauthoridLai, PT=7202946460en_HK
dc.identifier.scopusauthoridXu, JP=7407004696en_HK
dc.identifier.scopusauthoridChan, CL=8507083700en_HK

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