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Article: A threshold-voltage model of SiGe-channel pMOSFET without Si cap layer

TitleA threshold-voltage model of SiGe-channel pMOSFET without Si cap layer
Authors
Zou, XXu, JPLi, CXLai, PTChen, WB
Issue Date2007
PublisherPergamon. The Journal's web site is located at http://www.elsevier.com/locate/microrel
Citation
Microelectronics Reliability, 2007, v. 47 n. 2-3, p. 391-394 How to Cite?
DOI: http://dx.doi.org/10.1016/j.microrel.2006.05.019
AbstractAn analytical model on the threshold voltage of SiGe-channel pMOSFET with high-κ gate dielectric is developed by solving the Poisson's equation. Energy-band offset induced by SiGe strained layer, short-channel effect and drain-induced barrier lowering effect are taken into account in the model. To evaluate the validity of the model, simulated results are compared with experimental data, and good agreements are obtained. This model can be used for the design of SiGe-channel pMOSFET, thus determining its optimal parameters. © 2006 Elsevier Ltd. All rights reserved.
Persistent Identifierhttp://hdl.handle.net/10722/155353
ISSN
0026-2714
2023 Impact Factor: 1.6
2023 SCImago Journal Rankings: 0.394
ISI Accession Number ID
WOS:000244598900034
References
References in Scopus

 

DC FieldValueLanguage
dc.contributor.authorZou, Xen_HK
dc.contributor.authorXu, JPen_HK
dc.contributor.authorLi, CXen_HK
dc.contributor.authorLai, PTen_HK
dc.contributor.authorChen, WBen_HK
dc.date.accessioned2012-08-08T08:33:02Z-
dc.date.available2012-08-08T08:33:02Z-
dc.date.issued2007en_HK
dc.identifier.citationMicroelectronics Reliability, 2007, v. 47 n. 2-3, p. 391-394en_HK
dc.identifier.issn0026-2714en_HK
dc.identifier.urihttp://hdl.handle.net/10722/155353-
dc.description.abstractAn analytical model on the threshold voltage of SiGe-channel pMOSFET with high-κ gate dielectric is developed by solving the Poisson's equation. Energy-band offset induced by SiGe strained layer, short-channel effect and drain-induced barrier lowering effect are taken into account in the model. To evaluate the validity of the model, simulated results are compared with experimental data, and good agreements are obtained. This model can be used for the design of SiGe-channel pMOSFET, thus determining its optimal parameters. © 2006 Elsevier Ltd. All rights reserved.en_HK
dc.languageengen_US
dc.publisherPergamon. The Journal's web site is located at http://www.elsevier.com/locate/microrelen_HK
dc.relation.ispartofMicroelectronics Reliabilityen_HK
dc.titleA threshold-voltage model of SiGe-channel pMOSFET without Si cap layeren_HK
dc.typeArticleen_HK
dc.identifier.emailXu, JP: jpxu@eee.hku.hken_HK
dc.identifier.emailLai, PT: laip@eee.hku.hken_HK
dc.identifier.authorityXu, JP=rp00197en_HK
dc.identifier.authorityLai, PT=rp00130en_HK
dc.description.naturelink_to_subscribed_fulltexten_US
dc.identifier.doi10.1016/j.microrel.2006.05.019en_HK
dc.identifier.scopuseid_2-s2.0-33846621101en_HK
dc.identifier.hkuros135364-
dc.relation.referenceshttp://www.scopus.com/mlt/select.url?eid=2-s2.0-33846621101&selection=ref&src=s&origin=recordpageen_HK
dc.identifier.volume47en_HK
dc.identifier.issue2-3en_HK
dc.identifier.spage391en_HK
dc.identifier.epage394en_HK
dc.identifier.isiWOS:000244598900034-
dc.publisher.placeUnited Kingdomen_HK
dc.identifier.scopusauthoridZou, X=23020170400en_HK
dc.identifier.scopusauthoridXu, JP=7407004696en_HK
dc.identifier.scopusauthoridLi, CX=22034888200en_HK
dc.identifier.scopusauthoridLai, PT=7202946460en_HK
dc.identifier.scopusauthoridChen, WB=15119171500en_HK
dc.identifier.issnl0026-2714-

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