File Download

There are no files associated with this item.

  Links for fulltext
     (May Require Subscription)
Supplementary

Article: A loop-based apparatus for at-speed self-testing

TitleA loop-based apparatus for at-speed self-testing
Authors
KeywordsAt-Speed Test
Built-In Self-Test
Multiple Input Shift Register
State Transition Graph
Issue Date2001
Citation
Journal Of Computer Science And Technology, 2001, v. 16 n. 3, p. 278-285 How to Cite?
AbstractAt-speed testing using external tester requires an expensive equipment, thus built-in self-test (BIST) is an alternative technique due to its ability to perform on-chip at-speed self-testing. The main issue in BIST for at-speed testing is to obtain high delay fault coverage with a low hardware overhead. This paper presents an improved loop-based BIST scheme, in which a configurable MISR (multiple-input signature register) is used to generate test-pair sequences. The structure and operation modes of the BIST scheme are described. The topological properties of the state-transition-graph of the proposed BIST scheme are analyzed. Based on it, an approach to design and efficiently implement the proposed BIST scheme is developed. Experimental results on academic benchmark circuits are presented to demonstrate the effectiveness of the proposed BIST scheme as well as the design approach.
Persistent Identifierhttp://hdl.handle.net/10722/155147
ISSN
2015 Impact Factor: 0.475
2015 SCImago Journal Rankings: 0.437
References

 

DC FieldValueLanguage
dc.contributor.authorLi, Xen_US
dc.contributor.authorCheung, PYSen_US
dc.date.accessioned2012-08-08T08:32:04Z-
dc.date.available2012-08-08T08:32:04Z-
dc.date.issued2001en_US
dc.identifier.citationJournal Of Computer Science And Technology, 2001, v. 16 n. 3, p. 278-285en_US
dc.identifier.issn1000-9000en_US
dc.identifier.urihttp://hdl.handle.net/10722/155147-
dc.description.abstractAt-speed testing using external tester requires an expensive equipment, thus built-in self-test (BIST) is an alternative technique due to its ability to perform on-chip at-speed self-testing. The main issue in BIST for at-speed testing is to obtain high delay fault coverage with a low hardware overhead. This paper presents an improved loop-based BIST scheme, in which a configurable MISR (multiple-input signature register) is used to generate test-pair sequences. The structure and operation modes of the BIST scheme are described. The topological properties of the state-transition-graph of the proposed BIST scheme are analyzed. Based on it, an approach to design and efficiently implement the proposed BIST scheme is developed. Experimental results on academic benchmark circuits are presented to demonstrate the effectiveness of the proposed BIST scheme as well as the design approach.en_US
dc.languageengen_US
dc.relation.ispartofJournal of Computer Science and Technologyen_US
dc.subjectAt-Speed Testen_US
dc.subjectBuilt-In Self-Testen_US
dc.subjectMultiple Input Shift Registeren_US
dc.subjectState Transition Graphen_US
dc.titleA loop-based apparatus for at-speed self-testingen_US
dc.typeArticleen_US
dc.identifier.emailCheung, PYS:paul.cheung@hku.hken_US
dc.identifier.authorityCheung, PYS=rp00077en_US
dc.description.naturelink_to_subscribed_fulltexten_US
dc.identifier.doi10.1007/BF02943206-
dc.identifier.scopuseid_2-s2.0-0035335749en_US
dc.identifier.hkuros83137-
dc.relation.referenceshttp://www.scopus.com/mlt/select.url?eid=2-s2.0-0035335749&selection=ref&src=s&origin=recordpageen_US
dc.identifier.volume16en_US
dc.identifier.issue3en_US
dc.identifier.spage278en_US
dc.identifier.epage285en_US
dc.publisher.placeUnited Statesen_US
dc.identifier.scopusauthoridLi, X=8228906100en_US
dc.identifier.scopusauthoridCheung, PYS=7202595335en_US

Export via OAI-PMH Interface in XML Formats


OR


Export to Other Non-XML Formats