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Article: LFSR-based deterministic TPG for two-pattern testing

TitleLFSR-based deterministic TPG for two-pattern testing
Authors
Issue Date2000
PublisherSpringer New York LLC. The Journal's web site is located at http://springerlink.metapress.com/openurl.asp?genre=journal&issn=0923-8174
Citation
Journal Of Electronic Testing: Theory And Applications (Jetta), 2000, v. 16 n. 5, p. 419-426 How to Cite?
AbstractThis paper proposes an approach to designing a cost-effective deterministic test pattern generator (TPG) for two-pattern testing. Given a set of pre-generated test-pair set (obtained by an ATPG tool) with a pre-determined (path delay) fault coverage, a simple TPG is synthesized to apply the given test-pair set in a minimal test time. To achieve this objective, a configurable linear feedback shift register (CLFSR) structure is used. Techniques are developed to synthesize such a TPG, which is used to generate an unordered deterministic test-pair set. The resulting TPG is efficient in terms of hardware size and speed performance. Experiments on benchmark circuits indicate that TPG designed using the proposed procedure obtain high path delay fault coverage in short test length.
Persistent Identifierhttp://hdl.handle.net/10722/155134
ISSN
2015 Impact Factor: 0.361
2015 SCImago Journal Rankings: 0.372
ISI Accession Number ID
References

 

DC FieldValueLanguage
dc.contributor.authorLi, Xen_US
dc.contributor.authorCheung, PYSen_US
dc.contributor.authorFujiwara, Hen_US
dc.date.accessioned2012-08-08T08:32:00Z-
dc.date.available2012-08-08T08:32:00Z-
dc.date.issued2000en_US
dc.identifier.citationJournal Of Electronic Testing: Theory And Applications (Jetta), 2000, v. 16 n. 5, p. 419-426en_US
dc.identifier.issn0923-8174en_US
dc.identifier.urihttp://hdl.handle.net/10722/155134-
dc.description.abstractThis paper proposes an approach to designing a cost-effective deterministic test pattern generator (TPG) for two-pattern testing. Given a set of pre-generated test-pair set (obtained by an ATPG tool) with a pre-determined (path delay) fault coverage, a simple TPG is synthesized to apply the given test-pair set in a minimal test time. To achieve this objective, a configurable linear feedback shift register (CLFSR) structure is used. Techniques are developed to synthesize such a TPG, which is used to generate an unordered deterministic test-pair set. The resulting TPG is efficient in terms of hardware size and speed performance. Experiments on benchmark circuits indicate that TPG designed using the proposed procedure obtain high path delay fault coverage in short test length.en_US
dc.languageengen_US
dc.publisherSpringer New York LLC. The Journal's web site is located at http://springerlink.metapress.com/openurl.asp?genre=journal&issn=0923-8174en_US
dc.relation.ispartofJournal of Electronic Testing: Theory and Applications (JETTA)en_US
dc.titleLFSR-based deterministic TPG for two-pattern testingen_US
dc.typeArticleen_US
dc.identifier.emailCheung, PYS:paul.cheung@hku.hken_US
dc.identifier.authorityCheung, PYS=rp00077en_US
dc.description.naturelink_to_subscribed_fulltexten_US
dc.identifier.doi10.1023/A:1008356313212en_US
dc.identifier.scopuseid_2-s2.0-0034298661en_US
dc.relation.referenceshttp://www.scopus.com/mlt/select.url?eid=2-s2.0-0034298661&selection=ref&src=s&origin=recordpageen_US
dc.identifier.volume16en_US
dc.identifier.issue5en_US
dc.identifier.spage419en_US
dc.identifier.epage426en_US
dc.identifier.isiWOS:000089239600004-
dc.publisher.placeUnited Statesen_US
dc.identifier.scopusauthoridLi, X=8228906100en_US
dc.identifier.scopusauthoridCheung, PYS=7202595335en_US
dc.identifier.scopusauthoridFujiwara, H=7403718357en_US

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