Energy levels of interface states generated in n-MOSFETs by hot-carrier stresses

Abstract

The energy levels of interface states generated in n-MOSFETs during hot-carrier stressings under maximum substrate-current condition (VG approx. VD/2) are studied by measuring their GIDL current, which is believed to result from trap-assisted tunneling. It is found that different VG results in interface-state distribution with different energy-level edges in the forbidden gap. This phenomenon gives a new insight on the mechanism of interface-state generation: the energy release when holes are neutralized by electrons during stressing, depends on the energy the carriers obtain from the stress field which is related to VG and VD. Smaller released energy prefers to break those bonds with lower binding energy (e.g. strained Si-O bonds) and thus creates shallow interface states and vice versa. Hence, the effects of these shallow interface states on device reliabilities are a major concern because they would be highly created by the low operating voltage of MOSFETs. In addition, it is suggested that interface traps which are most effective in assisted tunneling are those closest to the mid-gap from the analyses on the barrier height of tunneling.