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Article: Programmable image processing system using FPGAs

TitleProgrammable image processing system using FPGAs
Authors
Issue Date1993
PublisherTaylor & Francis Ltd. The Journal's web site is located at http://www.tandf.co.uk/journals/titles/00207217.asp
Citation
International Journal Of Electronics, 1993, v. 75 n. 4, p. 725-730 How to Cite?
AbstractReal-time image processing usually requires an enormous throughput rate and a huge number of operations. Parallel processing, in the form of specialized hardware, or multiprocessing are therefore indispensable. This paper describes a flexible programmable image processing system using the field programmable gate array (FPGA). The logic cell nature of currently available FPGA is most suitable for performing real-time bit-level image processing operations using the bit-level systolic concept. Here, we propose a novel architecture, the programmable image processing system (PIPS), for the integration of these programmable hardware and digital signal processors (DSPs) to handle the bit-level as well as the arithmetic operations found in many image processing applications. The versatility of the system is demonstrated by the implementation of a 1-D median filter.
Persistent Identifierhttp://hdl.handle.net/10722/154989
ISSN
2015 Impact Factor: 0.414
2015 SCImago Journal Rankings: 0.221

 

DC FieldValueLanguage
dc.contributor.authorChan, SCen_US
dc.contributor.authorNgai, HOen_US
dc.contributor.authorHo, KLen_US
dc.date.accessioned2012-08-08T08:31:25Z-
dc.date.available2012-08-08T08:31:25Z-
dc.date.issued1993en_US
dc.identifier.citationInternational Journal Of Electronics, 1993, v. 75 n. 4, p. 725-730en_US
dc.identifier.issn0020-7217en_US
dc.identifier.urihttp://hdl.handle.net/10722/154989-
dc.description.abstractReal-time image processing usually requires an enormous throughput rate and a huge number of operations. Parallel processing, in the form of specialized hardware, or multiprocessing are therefore indispensable. This paper describes a flexible programmable image processing system using the field programmable gate array (FPGA). The logic cell nature of currently available FPGA is most suitable for performing real-time bit-level image processing operations using the bit-level systolic concept. Here, we propose a novel architecture, the programmable image processing system (PIPS), for the integration of these programmable hardware and digital signal processors (DSPs) to handle the bit-level as well as the arithmetic operations found in many image processing applications. The versatility of the system is demonstrated by the implementation of a 1-D median filter.en_US
dc.languageengen_US
dc.publisherTaylor & Francis Ltd. The Journal's web site is located at http://www.tandf.co.uk/journals/titles/00207217.aspen_US
dc.relation.ispartofInternational Journal of Electronicsen_US
dc.titleProgrammable image processing system using FPGAsen_US
dc.typeArticleen_US
dc.identifier.emailChan, SC:scchan@eee.hku.hken_US
dc.identifier.emailHo, KL:klho@eee.hku.hken_US
dc.identifier.authorityChan, SC=rp00094en_US
dc.identifier.authorityHo, KL=rp00117en_US
dc.description.naturelink_to_subscribed_fulltexten_US
dc.identifier.scopuseid_2-s2.0-0027683976en_US
dc.identifier.volume75en_US
dc.identifier.issue4en_US
dc.identifier.spage725en_US
dc.identifier.epage730en_US
dc.publisher.placeUnited Kingdomen_US
dc.identifier.scopusauthoridChan, SC=13310287100en_US
dc.identifier.scopusauthoridNgai, HO=6602732278en_US
dc.identifier.scopusauthoridHo, KL=7403581592en_US

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