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Article: RECURSIVE ADDITION AND ITS PARAMETERIZATION IN VLSI.

TitleRECURSIVE ADDITION AND ITS PARAMETERIZATION IN VLSI.
Authors
Issue Date1986
Citation
Iee Proceedings. Part G. Electronic Circuits And Systems, 1986, v. 133 n. 5, p. 256-264 How to Cite?
AbstractThis paper describes the specification, simulation and implementation of a parallel addition algorithm based on the recursive methodology. The features of this recursive addition algorithm are regularity, modularity, local interconnections, intensive pipelining and concurrency which are advantageous in real-time signal processing. The recursivity of the approach to be described allows high-level addition structures to be parameterized and built into a silicon compilation environment which may facilitate design automation in VLSI signal processing. The algorithm has been proven by a mixed-mode simulation which shows a favorable 155. 5 ns worst case bandwidth at 1. 56 w power dissipation for a 32-bit 5 mu m NMOS version. Comparison of the recursive algorithm with carry lookahead addition (CLA), carry propagate addition (CPA), Brent/Kung CLA, conditional sum addition and carry select addition is in favor of the recursive addition at word sizes smaller or equal to 16.
Persistent Identifierhttp://hdl.handle.net/10722/154861
ISSN

 

DC FieldValueLanguage
dc.contributor.authorYung, HCen_US
dc.contributor.authorAllen, CRen_US
dc.date.accessioned2012-08-08T08:30:57Z-
dc.date.available2012-08-08T08:30:57Z-
dc.date.issued1986en_US
dc.identifier.citationIee Proceedings. Part G. Electronic Circuits And Systems, 1986, v. 133 n. 5, p. 256-264en_US
dc.identifier.issn0143-7089en_US
dc.identifier.urihttp://hdl.handle.net/10722/154861-
dc.description.abstractThis paper describes the specification, simulation and implementation of a parallel addition algorithm based on the recursive methodology. The features of this recursive addition algorithm are regularity, modularity, local interconnections, intensive pipelining and concurrency which are advantageous in real-time signal processing. The recursivity of the approach to be described allows high-level addition structures to be parameterized and built into a silicon compilation environment which may facilitate design automation in VLSI signal processing. The algorithm has been proven by a mixed-mode simulation which shows a favorable 155. 5 ns worst case bandwidth at 1. 56 w power dissipation for a 32-bit 5 mu m NMOS version. Comparison of the recursive algorithm with carry lookahead addition (CLA), carry propagate addition (CPA), Brent/Kung CLA, conditional sum addition and carry select addition is in favor of the recursive addition at word sizes smaller or equal to 16.en_US
dc.languageengen_US
dc.relation.ispartofIEE proceedings. Part G. Electronic circuits and systemsen_US
dc.titleRECURSIVE ADDITION AND ITS PARAMETERIZATION IN VLSI.en_US
dc.typeArticleen_US
dc.identifier.emailYung, HC:nyung@eee.hku.hken_US
dc.identifier.authorityYung, HC=rp00226en_US
dc.description.naturelink_to_subscribed_fulltexten_US
dc.identifier.scopuseid_2-s2.0-0022793061en_US
dc.identifier.volume133en_US
dc.identifier.issue5en_US
dc.identifier.spage256en_US
dc.identifier.epage264en_US
dc.identifier.scopusauthoridYung, HC=7003473369en_US
dc.identifier.scopusauthoridAllen, CR=7402266059en_US

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