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Article: A recursive design methodology for VLSI: Theory and example

TitleA recursive design methodology for VLSI: Theory and example
Authors
KeywordsArchitectural Hierarchy
Area-Time Complexity
Convolution
Hierarchical Multiplication
Issue Date1984
PublisherElsevier BV. The Journal's web site is located at http://www.elsevier.com/locate/vlsi
Citation
Integration, The Vlsi Journal, 1984, v. 2 n. 3, p. 213-225 How to Cite?
AbstractA novel VLSI (Very Large Scale Integration) methodology based on the hierarchical design of computational and system blocks is presented. The underlying algorithms used are shown to optimise the area-time complexity (AT2) of the computational units and at the system design level. The technique is illustrated for a matrix-matrix multiplication by using an image processing window convolver. This paper describes the performance of the recursive design technique comparing it to a typical systolic array, and demonstrates how data word size and convolution size may be expanded by movement up the architectural hierarchy. A prototype CAD (Computer Aided Design) autolayout program is described which maps directly into the hierarchical design environment. Using such design aids, flexible and correct designs may be generated which offer very simple data flow and highly local interconnection, with high performance. © 1984.
Persistent Identifierhttp://hdl.handle.net/10722/154834
ISSN
2015 Impact Factor: 0.703
2015 SCImago Journal Rankings: 0.283

 

DC FieldValueLanguage
dc.contributor.authorYung, HCen_US
dc.contributor.authorAllen, CRen_US
dc.contributor.authorLiesenberg, HKEen_US
dc.contributor.authorKinniment, DJen_US
dc.date.accessioned2012-08-08T08:30:51Z-
dc.date.available2012-08-08T08:30:51Z-
dc.date.issued1984en_US
dc.identifier.citationIntegration, The Vlsi Journal, 1984, v. 2 n. 3, p. 213-225en_US
dc.identifier.issn0167-9260en_US
dc.identifier.urihttp://hdl.handle.net/10722/154834-
dc.description.abstractA novel VLSI (Very Large Scale Integration) methodology based on the hierarchical design of computational and system blocks is presented. The underlying algorithms used are shown to optimise the area-time complexity (AT2) of the computational units and at the system design level. The technique is illustrated for a matrix-matrix multiplication by using an image processing window convolver. This paper describes the performance of the recursive design technique comparing it to a typical systolic array, and demonstrates how data word size and convolution size may be expanded by movement up the architectural hierarchy. A prototype CAD (Computer Aided Design) autolayout program is described which maps directly into the hierarchical design environment. Using such design aids, flexible and correct designs may be generated which offer very simple data flow and highly local interconnection, with high performance. © 1984.en_US
dc.languageengen_US
dc.publisherElsevier BV. The Journal's web site is located at http://www.elsevier.com/locate/vlsien_US
dc.relation.ispartofIntegration, the VLSI Journalen_US
dc.subjectArchitectural Hierarchyen_US
dc.subjectArea-Time Complexityen_US
dc.subjectConvolutionen_US
dc.subjectHierarchical Multiplicationen_US
dc.titleA recursive design methodology for VLSI: Theory and exampleen_US
dc.typeArticleen_US
dc.identifier.emailYung, HC:nyung@eee.hku.hken_US
dc.identifier.authorityYung, HC=rp00226en_US
dc.description.naturelink_to_subscribed_fulltexten_US
dc.identifier.scopuseid_2-s2.0-0021484175en_US
dc.identifier.volume2en_US
dc.identifier.issue3en_US
dc.identifier.spage213en_US
dc.identifier.epage225en_US
dc.publisher.placeNetherlandsen_US
dc.identifier.scopusauthoridYung, HC=7003473369en_US
dc.identifier.scopusauthoridAllen, CR=7402266059en_US
dc.identifier.scopusauthoridLiesenberg, HKE=6506901845en_US
dc.identifier.scopusauthoridKinniment, DJ=7004755682en_US

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