File Download

There are no files associated with this item.

  Links for fulltext
     (May Require Subscription)
Supplementary

Article: OPTIMISING ANALYSIS OF HIERARCHICAL MULTIPLIERS FOR VLSI - PART 2.

TitleOPTIMISING ANALYSIS OF HIERARCHICAL MULTIPLIERS FOR VLSI - PART 2.
Authors
Yung, HCAllen, CR
KeywordsComplexity theory
Hierarchical multipliers
Very large scale integration
Issue Date1984
Citation
Iee Proceedings, Part G: Electronic Circuits And Systems, 1984, v. 131 n. 2, p. 61-66 How to Cite?
AbstractAn analysis of area-time complexity is presented for a specific hierarchical-multiplier design. The analysis is generally applicable to a variety of multiplier designs having hierarchical structure and may be used as a basic analytical tool for other arithmetic structures with hierarchy. Area and time performance are derived in terms of branching ratio. It is found the optimal area-time complexity is obtained for a branching ratio of four.
Persistent Identifierhttp://hdl.handle.net/10722/154828
ISSN
0143-7089
ISI Accession Number ID
WOS:A1984SL81700005

 

DC FieldValueLanguage
dc.contributor.authorYung, HCen_US
dc.contributor.authorAllen, CRen_US
dc.date.accessioned2012-08-08T08:30:50Z-
dc.date.available2012-08-08T08:30:50Z-
dc.date.issued1984en_US
dc.identifier.citationIee Proceedings, Part G: Electronic Circuits And Systems, 1984, v. 131 n. 2, p. 61-66en_US
dc.identifier.issn0143-7089en_US
dc.identifier.urihttp://hdl.handle.net/10722/154828-
dc.description.abstractAn analysis of area-time complexity is presented for a specific hierarchical-multiplier design. The analysis is generally applicable to a variety of multiplier designs having hierarchical structure and may be used as a basic analytical tool for other arithmetic structures with hierarchy. Area and time performance are derived in terms of branching ratio. It is found the optimal area-time complexity is obtained for a branching ratio of four.en_US
dc.languageengen_US
dc.relation.ispartofIEE Proceedings, Part G: Electronic Circuits and Systemsen_US
dc.subjectComplexity theory-
dc.subjectHierarchical multipliers-
dc.subjectVery large scale integration-
dc.titleOPTIMISING ANALYSIS OF HIERARCHICAL MULTIPLIERS FOR VLSI - PART 2.en_US
dc.typeArticleen_US
dc.identifier.emailYung, HC:nyung@eee.hku.hken_US
dc.identifier.authorityYung, HC=rp00226en_US
dc.description.naturelink_to_subscribed_fulltexten_US
dc.identifier.scopuseid_2-s2.0-0021410623en_US
dc.identifier.volume131en_US
dc.identifier.issue2en_US
dc.identifier.spage61en_US
dc.identifier.epage66en_US
dc.identifier.isiWOS:A1984SL81700005-
dc.identifier.scopusauthoridYung, HC=7003473369en_US
dc.identifier.scopusauthoridAllen, CR=7402266059en_US
dc.identifier.issnl0143-7089-

Export via OAI-PMH Interface in XML Formats

OR

Export to Other Non-XML Formats