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Article: Optimal floating point multiplication processor for signal processing

TitleOptimal floating point multiplication processor for signal processing
Authors
KeywordsArray Processor Design
Hierarchical Design Methodology
Vlsi Structures
Issue Date1983
PublisherElsevier BV. The Journal's web site is located at http://www.elsevier.com/locate/imavis
Citation
Image And Vision Computing, 1983, v. 1 n. 3, p. 152-156 How to Cite?
AbstractThe design of a floating point matrix- vector multiplication processor array for VLSI, which has an optimal area-time complexity product, is presented. This processor array is capable of performing the function yn = ∑ i=1 Nainxi (where n = 1,..., N) and can be applied in many digital signal processing applications, by simply changing the matrix coefficients stored in that array. Each N-bit mantissa, M-bit exponent (N, M) processor element of the array comprises a mantissa multiplier/adder circuit and hardware to handle the floating point control. The multiplier/adder circuit is implemented by a new optimal algorithm, which is regular, recursive and fast. Secondly, the algorithm offers a highly local and regular interconnection network, which is a fundamental requirement in VLSI circuit design methodology. © 1983.
Persistent Identifierhttp://hdl.handle.net/10722/154822
ISSN
2015 Impact Factor: 1.766
2015 SCImago Journal Rankings: 1.700

 

DC FieldValueLanguage
dc.contributor.authorYung, Hen_US
dc.contributor.authorAllen, Cen_US
dc.date.accessioned2012-08-08T08:30:48Z-
dc.date.available2012-08-08T08:30:48Z-
dc.date.issued1983en_US
dc.identifier.citationImage And Vision Computing, 1983, v. 1 n. 3, p. 152-156en_US
dc.identifier.issn0262-8856en_US
dc.identifier.urihttp://hdl.handle.net/10722/154822-
dc.description.abstractThe design of a floating point matrix- vector multiplication processor array for VLSI, which has an optimal area-time complexity product, is presented. This processor array is capable of performing the function yn = ∑ i=1 Nainxi (where n = 1,..., N) and can be applied in many digital signal processing applications, by simply changing the matrix coefficients stored in that array. Each N-bit mantissa, M-bit exponent (N, M) processor element of the array comprises a mantissa multiplier/adder circuit and hardware to handle the floating point control. The multiplier/adder circuit is implemented by a new optimal algorithm, which is regular, recursive and fast. Secondly, the algorithm offers a highly local and regular interconnection network, which is a fundamental requirement in VLSI circuit design methodology. © 1983.en_US
dc.languageengen_US
dc.publisherElsevier BV. The Journal's web site is located at http://www.elsevier.com/locate/imavisen_US
dc.relation.ispartofImage and Vision Computingen_US
dc.subjectArray Processor Designen_US
dc.subjectHierarchical Design Methodologyen_US
dc.subjectVlsi Structuresen_US
dc.titleOptimal floating point multiplication processor for signal processingen_US
dc.typeArticleen_US
dc.identifier.emailYung, H:nyung@eee.hku.hken_US
dc.identifier.authorityYung, H=rp00226en_US
dc.description.naturelink_to_subscribed_fulltexten_US
dc.identifier.scopuseid_2-s2.0-0020797056en_US
dc.identifier.volume1en_US
dc.identifier.issue3en_US
dc.identifier.spage152en_US
dc.identifier.epage156en_US
dc.publisher.placeNetherlandsen_US
dc.identifier.scopusauthoridYung, H=7003473369en_US
dc.identifier.scopusauthoridAllen, C=7402266059en_US

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