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Article: Minimization of the offset voltage in heterojunction dipolar transistors by using a thick spacer

TitleMinimization of the offset voltage in heterojunction dipolar transistors by using a thick spacer
Authors
Issue Date1993
PublisherAmerican Institute of Physics. The Journal's web site is located at http://apl.aip.org/
Citation
Applied Physics Letters, 1993, v. 62 n. 24, p. 3129-3131 How to Cite?
AbstractWe have successfully fabricated and characterized two-dimensional electron gas emitter heterojunction bipolar transistors (2DEG emitter HBTs) of AlInAs/InGaAs and AlGaAs/GaAs compound materials. With a 50 nm thick undoped InGaAs spacer employed in the emitter junction, the offset voltage of the AlInAs/InGaAs HBT is reduced from 500 to 70 mV. Experimental data of the offset voltage obtained at different spacer thickness show that a spacer of 30 nm would be optimum for both AlGaAs/GaAs and AlInAs/InGaAs HBTs. This is basically in agreement with the numerical calculation of the electron sheet density of the 2DEG. The reduction of the offset voltage by using a 2DEG emitter is particularly important for the AlInGa/InGaAs or InP/InGaAs HBTs, since the breakdown voltage of these devices is usually low and the composition grading in the emitter is either very complicated or not applicable.
Persistent Identifierhttp://hdl.handle.net/10722/154773
ISSN
2015 Impact Factor: 3.142
2015 SCImago Journal Rankings: 1.105
ISI Accession Number ID

 

DC FieldValueLanguage
dc.contributor.authorWang, Qen_US
dc.contributor.authorYang, ESen_US
dc.contributor.authorChen, YKen_US
dc.contributor.authorSivco, Den_US
dc.contributor.authorCho, AYen_US
dc.date.accessioned2012-08-08T08:30:35Z-
dc.date.available2012-08-08T08:30:35Z-
dc.date.issued1993en_US
dc.identifier.citationApplied Physics Letters, 1993, v. 62 n. 24, p. 3129-3131en_US
dc.identifier.issn0003-6951en_US
dc.identifier.urihttp://hdl.handle.net/10722/154773-
dc.description.abstractWe have successfully fabricated and characterized two-dimensional electron gas emitter heterojunction bipolar transistors (2DEG emitter HBTs) of AlInAs/InGaAs and AlGaAs/GaAs compound materials. With a 50 nm thick undoped InGaAs spacer employed in the emitter junction, the offset voltage of the AlInAs/InGaAs HBT is reduced from 500 to 70 mV. Experimental data of the offset voltage obtained at different spacer thickness show that a spacer of 30 nm would be optimum for both AlGaAs/GaAs and AlInAs/InGaAs HBTs. This is basically in agreement with the numerical calculation of the electron sheet density of the 2DEG. The reduction of the offset voltage by using a 2DEG emitter is particularly important for the AlInGa/InGaAs or InP/InGaAs HBTs, since the breakdown voltage of these devices is usually low and the composition grading in the emitter is either very complicated or not applicable.en_US
dc.languageengen_US
dc.publisherAmerican Institute of Physics. The Journal's web site is located at http://apl.aip.org/en_US
dc.relation.ispartofApplied Physics Lettersen_US
dc.titleMinimization of the offset voltage in heterojunction dipolar transistors by using a thick spaceren_US
dc.typeArticleen_US
dc.identifier.emailYang, ES:esyang@hkueee.hku.hken_US
dc.identifier.authorityYang, ES=rp00199en_US
dc.description.naturelink_to_subscribed_fulltexten_US
dc.identifier.doi10.1063/1.109104en_US
dc.identifier.scopuseid_2-s2.0-0005620043en_US
dc.identifier.volume62en_US
dc.identifier.issue24en_US
dc.identifier.spage3129en_US
dc.identifier.epage3131en_US
dc.identifier.isiWOS:A1993LF99000023-
dc.publisher.placeUnited Statesen_US
dc.identifier.scopusauthoridWang, Q=7406911671en_US
dc.identifier.scopusauthoridYang, ES=7202021229en_US
dc.identifier.scopusauthoridChen, YK=7601439922en_US
dc.identifier.scopusauthoridSivco, D=35416187900en_US
dc.identifier.scopusauthoridCho, AY=35415551100en_US

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