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Conference Paper: A block-diagonal structured model reduction scheme for power grid networks

TitleA block-diagonal structured model reduction scheme for power grid networks
Authors
KeywordsError prones
Full dense
Industrial power
Krylov subspace
Lower cost
Issue Date2011
PublisherIEEE Computer Society. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/conhome.jsp?punumber=1000198
Citation
Design, Automation and Test in Europe Conference and Exhibition (DATE 2011), Grenoble, France, 14-18 March 2011. In Design, Automation, and Test in Europe Conference and Exhibition Proceedings, 2011, p. 44-49 How to Cite?
AbstractWe propose a block-diagonal structured model order reduction (BDSM) scheme for fast power grid analysis. Compared with existing power grid model order reduction (MOR) methods, BDSM has several advantages. First, unlike many power grid reductions that are based on terminal reduction and thus error-prone, BDSM utilizes an exact column-by-column moment matching to provide higher numerical accuracy. Second, with similar accuracy and macromodel size, BDSM generates very sparse block-diagonal reduced-order models (ROMs) for massive-port systems at a lower cost, whereas traditional algorithms such as PRIMA produce full dense models inefficient for the subsequent simulation. Third, different from those MOR schemes based on extended Krylov subspace (EKS) technique, BDSM is input-signal independent, so the resulting ROM is reusable under different excitations. Finally, due to its blockdiagonal structure, the obtained ROM can be simulated very fast. The accuracy and efficiency of BDSM are verified by industrial power grid benchmarks. © 2011 EDAA.
Persistent Identifierhttp://hdl.handle.net/10722/140207
ISBN
ISSN
References

 

DC FieldValueLanguage
dc.contributor.authorZhang, Zen_HK
dc.contributor.authorHu, Xen_HK
dc.contributor.authorCheng, CKen_HK
dc.contributor.authorWong, Nen_HK
dc.date.accessioned2011-09-23T06:08:50Z-
dc.date.available2011-09-23T06:08:50Z-
dc.date.issued2011en_HK
dc.identifier.citationDesign, Automation and Test in Europe Conference and Exhibition (DATE 2011), Grenoble, France, 14-18 March 2011. In Design, Automation, and Test in Europe Conference and Exhibition Proceedings, 2011, p. 44-49en_HK
dc.identifier.isbn978-3-9810801-7-9-
dc.identifier.issn1530-1591en_HK
dc.identifier.urihttp://hdl.handle.net/10722/140207-
dc.description.abstractWe propose a block-diagonal structured model order reduction (BDSM) scheme for fast power grid analysis. Compared with existing power grid model order reduction (MOR) methods, BDSM has several advantages. First, unlike many power grid reductions that are based on terminal reduction and thus error-prone, BDSM utilizes an exact column-by-column moment matching to provide higher numerical accuracy. Second, with similar accuracy and macromodel size, BDSM generates very sparse block-diagonal reduced-order models (ROMs) for massive-port systems at a lower cost, whereas traditional algorithms such as PRIMA produce full dense models inefficient for the subsequent simulation. Third, different from those MOR schemes based on extended Krylov subspace (EKS) technique, BDSM is input-signal independent, so the resulting ROM is reusable under different excitations. Finally, due to its blockdiagonal structure, the obtained ROM can be simulated very fast. The accuracy and efficiency of BDSM are verified by industrial power grid benchmarks. © 2011 EDAA.en_HK
dc.languageengen_US
dc.publisherIEEE Computer Society. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/conhome.jsp?punumber=1000198-
dc.relation.ispartofDesign, Automation, and Test in Europe Conference and Exhibition Proceedingsen_HK
dc.rightsDesign, Automation, and Test in Europe Conference and Exhibition Proceedings . Copyright © IEEE Computer Society.-
dc.rights©2011 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.-
dc.rightsCreative Commons: Attribution 3.0 Hong Kong License-
dc.subjectError prones-
dc.subjectFull dense-
dc.subjectIndustrial power-
dc.subjectKrylov subspace-
dc.subjectLower cost-
dc.titleA block-diagonal structured model reduction scheme for power grid networksen_HK
dc.typeConference_Paperen_HK
dc.identifier.emailZhang, Z: zzhang1@HKUSUC.hku.hken_HK
dc.identifier.emailWong, N: nwong@eee.hku.hk-
dc.identifier.authorityWong, N=rp00190en_HK
dc.description.naturepublished_or_final_version-
dc.identifier.scopuseid_2-s2.0-79957542643en_HK
dc.identifier.hkuros192309en_US
dc.relation.referenceshttp://www.scopus.com/mlt/select.url?eid=2-s2.0-79957542643&selection=ref&src=s&origin=recordpageen_HK
dc.identifier.spage44en_HK
dc.identifier.epage49en_HK
dc.publisher.placeUnited Statesen_HK
dc.description.otherDesign, Automation and Test in Europe Conference and Exhibition (DATE 2011), Grenoble, France, 14-18 March 2011. In Design, Automation, and Test in Europe Conference and Exhibition Proceedings, 2011, p. 44-49-
dc.identifier.scopusauthoridWong, N=35235551600en_HK
dc.identifier.scopusauthoridCheng, CK=7404797875en_HK
dc.identifier.scopusauthoridHu, X=39761521700en_HK
dc.identifier.scopusauthoridZhang, Z=35390468200en_HK

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