File Download
Links for fulltext
(May Require Subscription)
- Publisher Website: 10.1109/DATE.2011.5763014
- Scopus: eid_2-s2.0-79957542643
- WOS: WOS:000410278900009
- Find via
Supplementary
- Citations:
- Appears in Collections:
Conference Paper: A block-diagonal structured model reduction scheme for power grid networks
Title | A block-diagonal structured model reduction scheme for power grid networks |
---|---|
Authors | |
Keywords | Error prones Full dense Industrial power Krylov subspace Lower cost |
Issue Date | 2011 |
Publisher | IEEE Computer Society. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/conhome.jsp?punumber=1000198 |
Citation | Design, Automation and Test in Europe Conference and Exhibition (DATE 2011), Grenoble, France, 14-18 March 2011. In Design, Automation, and Test in Europe Conference and Exhibition Proceedings, 2011, p. 44-49 How to Cite? |
Abstract | We propose a block-diagonal structured model order reduction (BDSM) scheme for fast power grid analysis. Compared with existing power grid model order reduction (MOR) methods, BDSM has several advantages. First, unlike many power grid reductions that are based on terminal reduction and thus error-prone, BDSM utilizes an exact column-by-column moment matching to provide higher numerical accuracy. Second, with similar accuracy and macromodel size, BDSM generates very sparse block-diagonal reduced-order models (ROMs) for massive-port systems at a lower cost, whereas traditional algorithms such as PRIMA produce full dense models inefficient for the subsequent simulation. Third, different from those MOR schemes based on extended Krylov subspace (EKS) technique, BDSM is input-signal independent, so the resulting ROM is reusable under different excitations. Finally, due to its blockdiagonal structure, the obtained ROM can be simulated very fast. The accuracy and efficiency of BDSM are verified by industrial power grid benchmarks. © 2011 EDAA. |
Persistent Identifier | http://hdl.handle.net/10722/140207 |
ISBN | |
ISSN | |
ISI Accession Number ID | |
References |
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Zhang, Z | en_HK |
dc.contributor.author | Hu, X | en_HK |
dc.contributor.author | Cheng, CK | en_HK |
dc.contributor.author | Wong, N | en_HK |
dc.date.accessioned | 2011-09-23T06:08:50Z | - |
dc.date.available | 2011-09-23T06:08:50Z | - |
dc.date.issued | 2011 | en_HK |
dc.identifier.citation | Design, Automation and Test in Europe Conference and Exhibition (DATE 2011), Grenoble, France, 14-18 March 2011. In Design, Automation, and Test in Europe Conference and Exhibition Proceedings, 2011, p. 44-49 | en_HK |
dc.identifier.isbn | 978-3-9810801-7-9 | - |
dc.identifier.issn | 1530-1591 | en_HK |
dc.identifier.uri | http://hdl.handle.net/10722/140207 | - |
dc.description.abstract | We propose a block-diagonal structured model order reduction (BDSM) scheme for fast power grid analysis. Compared with existing power grid model order reduction (MOR) methods, BDSM has several advantages. First, unlike many power grid reductions that are based on terminal reduction and thus error-prone, BDSM utilizes an exact column-by-column moment matching to provide higher numerical accuracy. Second, with similar accuracy and macromodel size, BDSM generates very sparse block-diagonal reduced-order models (ROMs) for massive-port systems at a lower cost, whereas traditional algorithms such as PRIMA produce full dense models inefficient for the subsequent simulation. Third, different from those MOR schemes based on extended Krylov subspace (EKS) technique, BDSM is input-signal independent, so the resulting ROM is reusable under different excitations. Finally, due to its blockdiagonal structure, the obtained ROM can be simulated very fast. The accuracy and efficiency of BDSM are verified by industrial power grid benchmarks. © 2011 EDAA. | en_HK |
dc.language | eng | en_US |
dc.publisher | IEEE Computer Society. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/conhome.jsp?punumber=1000198 | - |
dc.relation.ispartof | Design, Automation, and Test in Europe Conference and Exhibition Proceedings | en_HK |
dc.subject | Error prones | - |
dc.subject | Full dense | - |
dc.subject | Industrial power | - |
dc.subject | Krylov subspace | - |
dc.subject | Lower cost | - |
dc.title | A block-diagonal structured model reduction scheme for power grid networks | en_HK |
dc.type | Conference_Paper | en_HK |
dc.identifier.email | Zhang, Z: zzhang1@HKUSUC.hku.hk | en_HK |
dc.identifier.email | Wong, N: nwong@eee.hku.hk | - |
dc.identifier.authority | Wong, N=rp00190 | en_HK |
dc.description.nature | link_to_subscribed_fulltext | - |
dc.identifier.doi | 10.1109/DATE.2011.5763014 | - |
dc.identifier.scopus | eid_2-s2.0-79957542643 | en_HK |
dc.identifier.hkuros | 192309 | en_US |
dc.relation.references | http://www.scopus.com/mlt/select.url?eid=2-s2.0-79957542643&selection=ref&src=s&origin=recordpage | en_HK |
dc.identifier.spage | 44 | en_HK |
dc.identifier.epage | 49 | en_HK |
dc.identifier.isi | WOS:000410278900009 | - |
dc.publisher.place | United States | en_HK |
dc.description.other | Design, Automation and Test in Europe Conference and Exhibition (DATE 2011), Grenoble, France, 14-18 March 2011. In Design, Automation, and Test in Europe Conference and Exhibition Proceedings, 2011, p. 44-49 | - |
dc.identifier.scopusauthorid | Wong, N=35235551600 | en_HK |
dc.identifier.scopusauthorid | Cheng, CK=7404797875 | en_HK |
dc.identifier.scopusauthorid | Hu, X=39761521700 | en_HK |
dc.identifier.scopusauthorid | Zhang, Z=35390468200 | en_HK |
dc.identifier.issnl | 1530-1591 | - |