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Article: Feedback-based scheduling for load-balanced two-stage switches

TitleFeedback-based scheduling for load-balanced two-stage switches
Authors
Keywordsfeedback-based switch
Load-balanced switch
two-stage switch
Issue Date2010
PublisherI E E E. The Journal's web site is located at http://www.comsoc.org/livepubs/net
Citation
Ieee/Acm Transactions On Networking, 2010, v. 18 n. 4, p. 1077-1090 How to Cite?
AbstractA framework for designing feedback-based scheduling algorithms is proposed for elegantly solving the notorious packet missequencing problem of a load-balanced switch. Unlike existing approaches, we show that the efforts made in load balancing and keeping packets in order can complement each other. Specifically, at each middle-stage port between the two switch fabrics of a load-balanced switch, only a single-packet buffer for each virtual output queueing (VOQ) is required. Although packets belonging to the same flow pass through different middle-stage VOQs, the delays they experience at different middle-stage ports will be identical. This is made possible by properly selecting and coordinating the two sequences of switch configurations to form a joint sequence with both staggered symmetry property and in-order packet delivery property. Based on the staggered symmetry property, an efficient feedback mechanism is designed to allow the right middle-stage port occupancy vector to be delivered to the right input port at the right time. As a result, the performance of load balancing as well as the switch throughput is significantly improved. We further extend this feedback mechanism to support the multicabinet implementation of a load-balanced switch, where the propagation delay between switch linecards and switch fabrics is nonnegligible. As compared to the existing load-balanced switch architectures and scheduling algorithms, our solutions impose a modest requirement on switch hardware, but consistently yield better delay-throughput performance. Last but not least, some extensions and refinements are made to address the scalability, implementation, and fairness issues of our solutions. © 2009 IEEE.
Persistent Identifierhttp://hdl.handle.net/10722/139274
ISSN
2015 Impact Factor: 2.186
2015 SCImago Journal Rankings: 1.795
ISI Accession Number ID
Funding AgencyGrant Number
Cisco Research Center
Funding Information:

Manuscript received November 28, 2008; revised June 12, 2009 and August 25, 2009; approved by IEEE/ACM TRANSACTION ON NETWORKING Editor C. S. Chang. First published December 28, 2009; current version published August 18, 2010. This work was supported in part by the Cisco Research Center.

References

 

DC FieldValueLanguage
dc.contributor.authorHu, Ben_HK
dc.contributor.authorYeung, KLen_HK
dc.date.accessioned2011-09-23T05:47:49Z-
dc.date.available2011-09-23T05:47:49Z-
dc.date.issued2010en_HK
dc.identifier.citationIeee/Acm Transactions On Networking, 2010, v. 18 n. 4, p. 1077-1090en_HK
dc.identifier.issn1063-6692en_HK
dc.identifier.urihttp://hdl.handle.net/10722/139274-
dc.description.abstractA framework for designing feedback-based scheduling algorithms is proposed for elegantly solving the notorious packet missequencing problem of a load-balanced switch. Unlike existing approaches, we show that the efforts made in load balancing and keeping packets in order can complement each other. Specifically, at each middle-stage port between the two switch fabrics of a load-balanced switch, only a single-packet buffer for each virtual output queueing (VOQ) is required. Although packets belonging to the same flow pass through different middle-stage VOQs, the delays they experience at different middle-stage ports will be identical. This is made possible by properly selecting and coordinating the two sequences of switch configurations to form a joint sequence with both staggered symmetry property and in-order packet delivery property. Based on the staggered symmetry property, an efficient feedback mechanism is designed to allow the right middle-stage port occupancy vector to be delivered to the right input port at the right time. As a result, the performance of load balancing as well as the switch throughput is significantly improved. We further extend this feedback mechanism to support the multicabinet implementation of a load-balanced switch, where the propagation delay between switch linecards and switch fabrics is nonnegligible. As compared to the existing load-balanced switch architectures and scheduling algorithms, our solutions impose a modest requirement on switch hardware, but consistently yield better delay-throughput performance. Last but not least, some extensions and refinements are made to address the scalability, implementation, and fairness issues of our solutions. © 2009 IEEE.en_HK
dc.languageengen_US
dc.publisherI E E E. The Journal's web site is located at http://www.comsoc.org/livepubs/neten_HK
dc.relation.ispartofIEEE/ACM Transactions on Networkingen_HK
dc.rightsIEEE/ACM Transactions on Networking. Copyright © IEEE.-
dc.rightsCreative Commons: Attribution 3.0 Hong Kong License-
dc.rights©2010 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.-
dc.subjectfeedback-based switchen_HK
dc.subjectLoad-balanced switchen_HK
dc.subjecttwo-stage switchen_HK
dc.titleFeedback-based scheduling for load-balanced two-stage switchesen_HK
dc.typeArticleen_HK
dc.identifier.openurlhttp://library.hku.hk:4550/resserv?sid=HKU:IR&issn=1063-6692&volume=18&issue=4&spage=1077&epage=1090&date=2010&atitle=Feedback-based+scheduling+for+load-balanced+two-stage+switches-
dc.identifier.emailYeung, KL:kyeung@eee.hku.hken_HK
dc.identifier.authorityYeung, KL=rp00204en_HK
dc.description.naturepublished_or_final_version-
dc.identifier.doi10.1109/TNET.2009.2037318en_HK
dc.identifier.scopuseid_2-s2.0-77955768744en_HK
dc.identifier.hkuros195077en_US
dc.relation.referenceshttp://www.scopus.com/mlt/select.url?eid=2-s2.0-77955768744&selection=ref&src=s&origin=recordpageen_HK
dc.identifier.volume18en_HK
dc.identifier.issue4en_HK
dc.identifier.spage1077en_HK
dc.identifier.epage1090en_HK
dc.identifier.isiWOS:000281113500006-
dc.publisher.placeUnited Statesen_HK
dc.identifier.scopusauthoridHu, B=36617158500en_HK
dc.identifier.scopusauthoridYeung, KL=7202424908en_HK

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