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Conference Paper: Dynamic power reduction of FPGA-based reconfigurable computers using precomputation

TitleDynamic power reduction of FPGA-based reconfigurable computers using precomputation
Authors
KeywordsField-programmable gate arrays
FPGAs
Reconfigurable computer
Precomputation
Dynamic power reduction
Issue Date2010
PublisherAssociation for Computing Machinery (ACM).
Citation
The 1st International Workshop on Highly Efficient Accelerators and Reconfigurable Technologies (HEART), Tsukuba, Japan, 1 June 2010. In ACM SIGARCH Computer Architecture News, 2010, v. 38 n. 4, p. 87-92 How to Cite?
AbstractThis paper examines the effectiveness of employing pre-computation techniques to reduce power consumption of field configurable computing systems. Multiplier is modified with pre-computation techniques and are implemented using commercial off-the-shelf FPGAs. Pre-computation techniques reduce dynamic power consumption of a module by eliminating unnecessary signal switching activities in inactive portions of the modules. Experiments have shown that up to 52% of logic and signal power consumption can be reduced in multiplier module. Furthermore, when compared to ASIC implementations, FPGA implementations of pre-computation modules have the advantage of lower area overhead as most of them can be implemented using originally unoccupied related FPGA resources. Finally, it was found that the effectiveness of pre-computation depends heavily on the input data statistics. It is expected that compilers for future reconfigurable computers may take full advantage of such power saving techniques by optimizing the architecture according to data input statistics.
Persistent Identifierhttp://hdl.handle.net/10722/135122
ISSN

 

DC FieldValueLanguage
dc.contributor.authorTsang, CCen_US
dc.contributor.authorSo, HKHen_US
dc.date.accessioned2011-07-27T01:28:33Z-
dc.date.available2011-07-27T01:28:33Z-
dc.date.issued2010en_US
dc.identifier.citationThe 1st International Workshop on Highly Efficient Accelerators and Reconfigurable Technologies (HEART), Tsukuba, Japan, 1 June 2010. In ACM SIGARCH Computer Architecture News, 2010, v. 38 n. 4, p. 87-92en_US
dc.identifier.issn0163-5964-
dc.identifier.urihttp://hdl.handle.net/10722/135122-
dc.description.abstractThis paper examines the effectiveness of employing pre-computation techniques to reduce power consumption of field configurable computing systems. Multiplier is modified with pre-computation techniques and are implemented using commercial off-the-shelf FPGAs. Pre-computation techniques reduce dynamic power consumption of a module by eliminating unnecessary signal switching activities in inactive portions of the modules. Experiments have shown that up to 52% of logic and signal power consumption can be reduced in multiplier module. Furthermore, when compared to ASIC implementations, FPGA implementations of pre-computation modules have the advantage of lower area overhead as most of them can be implemented using originally unoccupied related FPGA resources. Finally, it was found that the effectiveness of pre-computation depends heavily on the input data statistics. It is expected that compilers for future reconfigurable computers may take full advantage of such power saving techniques by optimizing the architecture according to data input statistics.-
dc.languageengen_US
dc.publisherAssociation for Computing Machinery (ACM).en_US
dc.relation.ispartofACM SIGARCH Computer Architecture Newsen_US
dc.rightsCreative Commons: Attribution 3.0 Hong Kong License-
dc.rightsACM SIGARCH Computer Architecture News. Copyright © Association for Computing Machinery.-
dc.rights© ACM, 2010. This is the author's version of the work. It is posted here by permission of ACM for your personal use. Not for redistribution. The definitive version was published in ACM SIGARCH Computer Architecture News, v. 38, no. 4, ISSN 0163-5964, September 2010 - http://doi.acm.org/10.1145/1926367.1926382-
dc.subjectField-programmable gate arrays-
dc.subjectFPGAs-
dc.subjectReconfigurable computer-
dc.subjectPrecomputation-
dc.subjectDynamic power reduction-
dc.titleDynamic power reduction of FPGA-based reconfigurable computers using precomputationen_US
dc.typeConference_Paperen_US
dc.identifier.openurlhttp://library.hku.hk:4550/resserv?sid=HKU:IR&issn=0163-5964&volume=38&issue=4&spage=87&epage=92&date=2010&atitle=Dynamic+power+reduction+of+FPGA-based+reconfigurable+computers+using+precomputation-
dc.identifier.emailTsang, CC: cctsang@eee.hku.hken_US
dc.identifier.emailSo, HKH: hso@eee.hku.hk-
dc.identifier.authoritySo, HKH=rp00169en_US
dc.description.naturepostprint-
dc.identifier.doi10.1145/1926367.1926382-
dc.identifier.hkuros187949en_US
dc.identifier.volume38en_US
dc.identifier.issue4-
dc.identifier.spage87en_US
dc.identifier.epage92en_US
dc.identifier.eissn1943-5851-
dc.description.otherThe 1st International Workshop on Highly Efficient Accelerators and Reconfigurable Technologies (HEART), Tsukuba, Japan, 1 June 2010. In ACM SIGARCH Computer Architecture News, 2010, v. 38 n. 4, p. 87-92-

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