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Conference Paper: Automatic system architecture synthesis for FPGA-based reconfigurable computers

TitleAutomatic system architecture synthesis for FPGA-based reconfigurable computers
Authors
Lin, CYWong, NSo, HKH
Issue Date2009
PublisherIEEE, Computer Society.
Citation
The 2009 International Conference on Field-Programmable Technology (FTP 2009), University of New South Wales Sydney, Australia, 9-11 December 2009. In Proceedings of the IEEE International Conference on FieId-Programmable Technology, 2009, p. 475-476 How to Cite?
DOI: http://dx.doi.org/10.1109/FPT.2009.5377691
AbstractThe goal of this PhD project is to develop an automatic method of system architecture synthesis for general high-performance applications on FPGA-based reconfigurable computers. Through our previous research, we have built a theoretical model targeting the scheduling problem with first-order hardware constraints. And a list scheduling algorithm is developed to achieve near-optimal performances. Currently, we are working on the low-level implementation. A systolic architecture is used, and the list scheduling algorithm will be extended to take into account constraints deriving from exact hardware architecture. (Abstract by, IEEE)
DescriptionIn Proceedings of the IEEE International Conference on FieId-Programmable Technology, 2009, p. 475-476
Persistent Identifierhttp://hdl.handle.net/10722/129739
ISBN
978-1-4244-4377-2
References
References in Scopus

 

DC FieldValueLanguage
dc.contributor.authorLin, CYen_HK
dc.contributor.authorWong, Nen_HK
dc.contributor.authorSo, HKHen_HK
dc.date.accessioned2010-12-23T08:41:24Z-
dc.date.available2010-12-23T08:41:24Z-
dc.date.issued2009en_HK
dc.identifier.citationThe 2009 International Conference on Field-Programmable Technology (FTP 2009), University of New South Wales Sydney, Australia, 9-11 December 2009. In Proceedings of the IEEE International Conference on FieId-Programmable Technology, 2009, p. 475-476en_HK
dc.identifier.isbn978-1-4244-4377-2-
dc.identifier.urihttp://hdl.handle.net/10722/129739-
dc.descriptionIn Proceedings of the IEEE International Conference on FieId-Programmable Technology, 2009, p. 475-476-
dc.description.abstractThe goal of this PhD project is to develop an automatic method of system architecture synthesis for general high-performance applications on FPGA-based reconfigurable computers. Through our previous research, we have built a theoretical model targeting the scheduling problem with first-order hardware constraints. And a list scheduling algorithm is developed to achieve near-optimal performances. Currently, we are working on the low-level implementation. A systolic architecture is used, and the list scheduling algorithm will be extended to take into account constraints deriving from exact hardware architecture. (Abstract by, IEEE)-
dc.languageengen_US
dc.publisherIEEE, Computer Society.-
dc.relation.ispartofProceedings of the 2009 International Conference on Field-Programmable Technology, FPT'09en_HK
dc.rights©2009 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.-
dc.titleAutomatic system architecture synthesis for FPGA-based reconfigurable computersen_HK
dc.typeConference_Paperen_HK
dc.identifier.emailWong, N:nwong@eee.hku.hken_HK
dc.identifier.emailSo, HKH:hso@eee.hku.hken_HK
dc.identifier.authorityWong, N=rp00190en_HK
dc.identifier.authoritySo, HKH=rp00169en_HK
dc.description.naturepublished_or_final_version-
dc.identifier.doi10.1109/FPT.2009.5377691en_HK
dc.identifier.scopuseid_2-s2.0-77949397307en_HK
dc.identifier.hkuros177866en_US
dc.relation.referenceshttp://www.scopus.com/mlt/select.url?eid=2-s2.0-77949397307&selection=ref&src=s&origin=recordpageen_HK
dc.identifier.spage475en_HK
dc.identifier.epage476en_HK
dc.publisher.placeUnited States-
dc.description.otherThe 2009 International Conference on Field-Programmable Technology (FTP 2009), University of New South Wales Sydney, Australia, 9-11 December 2009. In Proceedings of the IEEE International Conference on FieId-Programmable Technology, 2009, p. 475-476-
dc.identifier.scopusauthoridLin, CY=35177986900en_HK
dc.identifier.scopusauthoridWong, N=35235551600en_HK
dc.identifier.scopusauthoridSo, HKH=10738896800en_HK

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