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Conference Paper: Electrical modelling of temperature distributions in on-chip interconnects, packaging, and 3D integration

TitleElectrical modelling of temperature distributions in on-chip interconnects, packaging, and 3D integration
Authors
Keywords3D integration
Chip technology
Closed form
Critical region
Effective thermal conductivity
Issue Date2010
PublisherIEEE. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/conhome.jsp?punumber=1800046
Citation
2010 Asia-Pacific Symposium On Electromagnetic Compatibility, Apemc 2010, 2010, p. 625-628 How to Cite?
AbstractIn this talk, we will introduce a novel methodology using existing electromagnetic modelling tools for interconnect and packaging structures to simulate and model the temperature distribution without major modifications to these tools or simulated structures. This methodology can easily be integrated with the chip technology information and frame an electrical circuit simulator into an automatic, template-based simulation and optimization flow. A new accurate closed-form thermal model is further developed to simplify unnecessary object details. The model allows an equivalent medium with effective thermal conductivity (isotropic or anisotropic) to replace details in non-critical regions accurately so that complex interconnect structures can be simulated at a system level. Using these techniques, we demonstrate the modelling capability of very complex on-chip interconnects, packaging, and 3D integration technologies. © 2010 IEEE.
DescriptionProceedings of the International Symposium on Health Informatics and Bioinformatics, 2010, p. 625-628
Persistent Identifierhttp://hdl.handle.net/10722/126073
ISBN
References

 

DC FieldValueLanguage
dc.contributor.authorJiang, Len_HK
dc.contributor.authorXu, Cen_HK
dc.contributor.authorSmith, Hen_HK
dc.contributor.authorRubin, Ben_HK
dc.contributor.authorDeutsch, Aen_HK
dc.contributor.authorCaron, Aen_HK
dc.date.accessioned2010-10-31T12:08:20Z-
dc.date.available2010-10-31T12:08:20Z-
dc.date.issued2010en_HK
dc.identifier.citation2010 Asia-Pacific Symposium On Electromagnetic Compatibility, Apemc 2010, 2010, p. 625-628en_HK
dc.identifier.isbn978-1-4244-5621-5-
dc.identifier.urihttp://hdl.handle.net/10722/126073-
dc.descriptionProceedings of the International Symposium on Health Informatics and Bioinformatics, 2010, p. 625-628-
dc.description.abstractIn this talk, we will introduce a novel methodology using existing electromagnetic modelling tools for interconnect and packaging structures to simulate and model the temperature distribution without major modifications to these tools or simulated structures. This methodology can easily be integrated with the chip technology information and frame an electrical circuit simulator into an automatic, template-based simulation and optimization flow. A new accurate closed-form thermal model is further developed to simplify unnecessary object details. The model allows an equivalent medium with effective thermal conductivity (isotropic or anisotropic) to replace details in non-critical regions accurately so that complex interconnect structures can be simulated at a system level. Using these techniques, we demonstrate the modelling capability of very complex on-chip interconnects, packaging, and 3D integration technologies. © 2010 IEEE.en_HK
dc.languageengen_HK
dc.publisherIEEE. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/conhome.jsp?punumber=1800046-
dc.relation.ispartof2010 Asia-Pacific Symposium on Electromagnetic Compatibility, APEMC 2010en_HK
dc.rightsProceedings of the International Symposium on Health Informatics and Bioinformatics. Copyright © IEEE.-
dc.rightsCreative Commons: Attribution 3.0 Hong Kong License-
dc.rights©2010 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.-
dc.subject3D integration-
dc.subjectChip technology-
dc.subjectClosed form-
dc.subjectCritical region-
dc.subjectEffective thermal conductivity-
dc.titleElectrical modelling of temperature distributions in on-chip interconnects, packaging, and 3D integrationen_HK
dc.typeConference_Paperen_HK
dc.identifier.emailJiang, L:ljiang@eee.hku.hken_HK
dc.identifier.authorityJiang, L=rp01338en_HK
dc.description.naturepublished_or_final_version-
dc.identifier.doi10.1109/APEMC.2010.5475701en_HK
dc.identifier.scopuseid_2-s2.0-77955005383en_HK
dc.identifier.hkuros182542en_HK
dc.identifier.hkuros195282-
dc.relation.referenceshttp://www.scopus.com/mlt/select.url?eid=2-s2.0-77955005383&selection=ref&src=s&origin=recordpageen_HK
dc.identifier.spage625en_HK
dc.identifier.epage628en_HK
dc.identifier.scopusauthoridJiang, L=36077777200en_HK
dc.identifier.scopusauthoridXu, C=31767769100en_HK
dc.identifier.scopusauthoridSmith, H=7406226774en_HK
dc.identifier.scopusauthoridRubin, B=7201761344en_HK
dc.identifier.scopusauthoridDeutsch, A=7102025083en_HK
dc.identifier.scopusauthoridCaron, A=7005546788en_HK

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