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Article: A study on the improved programming characteristics of flash memory with Si 3N 4/SiO 2 stacked tunneling dielectric

TitleA study on the improved programming characteristics of flash memory with Si 3N 4/SiO 2 stacked tunneling dielectric
Authors
Issue Date2009
PublisherPergamon. The Journal's web site is located at http://www.elsevier.com/locate/microrel
Citation
Microelectronics Reliability, 2009, v. 49 n. 8, p. 912-915 How to Cite?
AbstractThe programming characteristics of memories with different tunneling-layer structures (Si 3N 4, SiO 2 and Si 3N 4/SiO 2 stack) dielectrics are investigated using 2-D device simulator of MEDICI. It is theoretically confirmed that the memory with the SiO 2/Si 3N 4 stacked tunneling layer exhibits better programming characteristics than ones with single tunneling layer of SiO 2 or Si 3N 4 for programming by channel hot electron (CHE) injection. A 10-μs programming time with a threshold-voltage shift of 5 V can be obtained for the memory with SiO 2/Si 3N 4 stacked tunneling layer at V cg = 10 V and V ds = 3.3 V. This is attributed to the fact that the floating-gate voltage is close to drain voltage for the stacked tunneling dielectric (TD), and thus the CHE injection current is the largest. Furthermore, optimal substrate concentration is determined to be 5 × 10 16-2 × 10 17 cm -3, by considering a trade-off between the programming characteristics and power dissipation/lifetime of the devices. Lastly, the effects of interface states on the programming characteristics are investigated. Low interface-state density gives short programming time and small post-programming control-gate current. © 2009 Elsevier Ltd. All rights reserved.
Persistent Identifierhttp://hdl.handle.net/10722/124744
ISSN
2015 Impact Factor: 1.202
2015 SCImago Journal Rankings: 0.675
ISI Accession Number ID
References

 

DC FieldValueLanguage
dc.contributor.authorLiu, Len_HK
dc.contributor.authorXu, JPen_HK
dc.contributor.authorChen, LLen_HK
dc.contributor.authorLai, PTen_HK
dc.date.accessioned2010-10-31T10:51:38Z-
dc.date.available2010-10-31T10:51:38Z-
dc.date.issued2009en_HK
dc.identifier.citationMicroelectronics Reliability, 2009, v. 49 n. 8, p. 912-915en_HK
dc.identifier.issn0026-2714en_HK
dc.identifier.urihttp://hdl.handle.net/10722/124744-
dc.description.abstractThe programming characteristics of memories with different tunneling-layer structures (Si 3N 4, SiO 2 and Si 3N 4/SiO 2 stack) dielectrics are investigated using 2-D device simulator of MEDICI. It is theoretically confirmed that the memory with the SiO 2/Si 3N 4 stacked tunneling layer exhibits better programming characteristics than ones with single tunneling layer of SiO 2 or Si 3N 4 for programming by channel hot electron (CHE) injection. A 10-μs programming time with a threshold-voltage shift of 5 V can be obtained for the memory with SiO 2/Si 3N 4 stacked tunneling layer at V cg = 10 V and V ds = 3.3 V. This is attributed to the fact that the floating-gate voltage is close to drain voltage for the stacked tunneling dielectric (TD), and thus the CHE injection current is the largest. Furthermore, optimal substrate concentration is determined to be 5 × 10 16-2 × 10 17 cm -3, by considering a trade-off between the programming characteristics and power dissipation/lifetime of the devices. Lastly, the effects of interface states on the programming characteristics are investigated. Low interface-state density gives short programming time and small post-programming control-gate current. © 2009 Elsevier Ltd. All rights reserved.en_HK
dc.languageengen_HK
dc.publisherPergamon. The Journal's web site is located at http://www.elsevier.com/locate/microrelen_HK
dc.relation.ispartofMicroelectronics Reliabilityen_HK
dc.titleA study on the improved programming characteristics of flash memory with Si 3N 4/SiO 2 stacked tunneling dielectricen_HK
dc.typeArticleen_HK
dc.identifier.openurlhttp://library.hku.hk:4550/resserv?sid=HKU:IR&issn=0026-2714&volume=49&spage=912&epage=915&date=2009&atitle=A+Study+on+the+Improved+Programming+Characteristics+of+Flash+Memory+with+Si3N4/SiO2+Stacked+Tunneling+Dielectricen_HK
dc.identifier.emailXu, JP: jpxu@eee.hku.hken_HK
dc.identifier.emailLai, PT: laip@eee.hku.hken_HK
dc.identifier.authorityXu, JP=rp00197en_HK
dc.identifier.authorityLai, PT=rp00130en_HK
dc.description.naturelink_to_subscribed_fulltext-
dc.identifier.doi10.1016/j.microrel.2009.05.010en_HK
dc.identifier.scopuseid_2-s2.0-67650357550en_HK
dc.identifier.hkuros179058en_HK
dc.relation.referenceshttp://www.scopus.com/mlt/select.url?eid=2-s2.0-67650357550&selection=ref&src=s&origin=recordpageen_HK
dc.identifier.volume49en_HK
dc.identifier.issue8en_HK
dc.identifier.spage912en_HK
dc.identifier.epage915en_HK
dc.identifier.isiWOS:000268984600013-
dc.publisher.placeUnited Kingdomen_HK
dc.identifier.scopusauthoridLiu, L=35778603700en_HK
dc.identifier.scopusauthoridXu, JP=7407004696en_HK
dc.identifier.scopusauthoridChen, LL=14024076100en_HK
dc.identifier.scopusauthoridLai, PT=7202946460en_HK

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