Optimising the Performance of SiC Devices Through the Control of Atomic Scale Deep Level Defect

Professor Ling, Francis Chi Chung   (Principal Investigator (PI))

Mr Ho Wing Kin   (Co-Investigator)

9

2021-09-01

2022-05-31

301500

Optimising the Performance of SiC Devices Through the Control of Atomic Scale Deep Level Defect

Atomic Scale Deep Level Defect, SiC Devices

Electronics

Physical Sciences (P)

PiH/335/21

Research Talent Hub for ITF Projects (RTH-ITF)

2021

Completed

In the applications of electrical vehicles, photovoltaic and power invertor for railway, SiC devices are now emerging as the most promising next power devices. Unlike the Si-based power devices, SiC based system have better energy efficiency, compactness and lighter weight. Ion implantation and the subsequent annealing are the key device fabrication procedures. However, these processes inevitably create atomic scale intrinsic defect (like the dominant one, carbon vacancy) which are electrical active deep traps leading to device performance deterioration. This leads to low yield and even higher unit cost for large chip size & high current rating SiC devices for these applications which shall grow above USD 20B market size in the next decade. Our preliminary study showed that re-annealing at a relatively low temperature after the ion-implanted dopant activation process resulted in suppression of carbon vacancy in the 4H-SiC materials. The present project studies the influence of the low-temperature re-annealing on the carbon vacancy and other deep level defects in the 4H-SiC diodes; aims to understand the physical mechanism and optimize the re-annealing conditions for suppressing the defects and enhancing the device performance and yield, thus, lower the cost and foster more energy saving SiC applications toward a greener world.