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Article: PACoGen: A Hardware Posit Arithmetic Core Generator

TitlePACoGen: A Hardware Posit Arithmetic Core Generator
Authors
KeywordsAdder
ASIC
Digital arithmetic
Division
Floating point arithmetic
FPGA
Multiplier
Posit arithmetic
Subtractor
Universal number system
Issue Date2019
PublisherInstitute of Electrical and Electronics Engineers (IEEE): OAJ. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=6287639
Citation
IEEE Access, 2019, v. 7, p. 74586-74601 How to Cite?
AbstractThis paper proposes open-source hardware Posit Arithmetic Core Generator (PACoGen) for the recently developed universal number posit number system, along with a set of pipelined architectures. The posit number system composed of a run-time varying exponent component, which is defined by a composition of varying length “regime-bit” and “exponent-bit” (with a maximum size of ES bits, the exponent size). This in effect also makes the fraction part to vary at run-time in size and position. These run-time variations inherit an interesting hardware design challenge for posit arithmetic architectures. The posit number system, being at an infant stage of its development, possess very limited hardware solutions for its arithmetic architectures. In this view, this paper targets the algorithmic development and generic HDL generators (PACoGen) for basic posit arithmetic. The proposed open source PACoGen currently includes the adder/subtractor, multiplier, and division arithmetic. The PACoGen can provide the Verilog HDL code respective posit arithmetic for any given posit word width (N) and exponent size (ES), as defined under the posit number system. Further, pipelined architectures of 32-bit posit with 6-bit exponent size are also proposed and discussed for addition/subtraction, multiplication, and division arithmetic. The proposed posit arithmetic architectures are demonstrated on the Virtex-7 (xc7vx330t-3ffg1157) FPGA device as well as Nangate 15 nm ASIC platform. The PACoGen would open a gateway for further posit arithmetic hardware exploration and evaluation.
Persistent Identifierhttp://hdl.handle.net/10722/275023
ISSN
2017 Impact Factor: 3.557
2015 SCImago Journal Rankings: 0.947
ISI Accession Number ID

 

DC FieldValueLanguage
dc.contributor.authorJaiswal, MK-
dc.contributor.authorSo, HKH-
dc.date.accessioned2019-09-10T02:33:52Z-
dc.date.available2019-09-10T02:33:52Z-
dc.date.issued2019-
dc.identifier.citationIEEE Access, 2019, v. 7, p. 74586-74601-
dc.identifier.issn2169-3536-
dc.identifier.urihttp://hdl.handle.net/10722/275023-
dc.description.abstractThis paper proposes open-source hardware Posit Arithmetic Core Generator (PACoGen) for the recently developed universal number posit number system, along with a set of pipelined architectures. The posit number system composed of a run-time varying exponent component, which is defined by a composition of varying length “regime-bit” and “exponent-bit” (with a maximum size of ES bits, the exponent size). This in effect also makes the fraction part to vary at run-time in size and position. These run-time variations inherit an interesting hardware design challenge for posit arithmetic architectures. The posit number system, being at an infant stage of its development, possess very limited hardware solutions for its arithmetic architectures. In this view, this paper targets the algorithmic development and generic HDL generators (PACoGen) for basic posit arithmetic. The proposed open source PACoGen currently includes the adder/subtractor, multiplier, and division arithmetic. The PACoGen can provide the Verilog HDL code respective posit arithmetic for any given posit word width (N) and exponent size (ES), as defined under the posit number system. Further, pipelined architectures of 32-bit posit with 6-bit exponent size are also proposed and discussed for addition/subtraction, multiplication, and division arithmetic. The proposed posit arithmetic architectures are demonstrated on the Virtex-7 (xc7vx330t-3ffg1157) FPGA device as well as Nangate 15 nm ASIC platform. The PACoGen would open a gateway for further posit arithmetic hardware exploration and evaluation.-
dc.languageeng-
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE): OAJ. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=6287639-
dc.relation.ispartofIEEE Access-
dc.rights© 2019 IEEE. Translations and content mining are permitted for academic research only. Personal use is also permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.-
dc.subjectAdder-
dc.subjectASIC-
dc.subjectDigital arithmetic-
dc.subjectDivision-
dc.subjectFloating point arithmetic-
dc.subjectFPGA-
dc.subjectMultiplier-
dc.subjectPosit arithmetic-
dc.subjectSubtractor-
dc.subjectUniversal number system-
dc.titlePACoGen: A Hardware Posit Arithmetic Core Generator-
dc.typeArticle-
dc.identifier.emailJaiswal, MK: manishkj@hku.hk-
dc.identifier.emailSo, HKH: hso@eee.hku.hk-
dc.identifier.authoritySo, HKH=rp00169-
dc.description.naturepublished_or_final_version-
dc.identifier.doi10.1109/ACCESS.2019.2920936-
dc.identifier.scopuseid_2-s2.0-85068239068-
dc.identifier.hkuros304135-
dc.identifier.volume7-
dc.identifier.spage74586-
dc.identifier.epage74601-
dc.identifier.isiWOS:000473188000001-
dc.publisher.placeUnited States-

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