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Conference Paper: Towards FPGA-assisted spark: An SVM training acceleration case study

TitleTowards FPGA-assisted spark: An SVM training acceleration case study
Authors
KeywordsSupport vector machines
Sparks
Field programmable gate arrays
Training
Acceleration
Issue Date2016
PublisherIEEE.
Citation
2016 International Conference on ReConFigurable Computing and FPGAs (ReConFig), Cancun, Mexico, 30 November-2 December 2016. In 2016 International Conference on ReConFigurable Computing and FPGAs (ReConFig), p. 1-6 How to Cite?
AbstractA system that augments the Apache Spark data processing framework with FPGA accelerators is presented as a way to model and deploy FPGA-assisted applications in large-scale clusters. In our proposed framework, FPGAs can optionally be used in place of the host CPU for Resilient distributed datasets (RDDs) transformations, allowing seamless integration between gateware and software processing. Using the case of training an Support Vector Machine (SVM) cell image classifier as a case study, we explore the feasibilities, benefits and challenges of such technique. In our experiments where data communication between CPU and FPGA is tightly controlled, a consistent speedup of up to 1.6x can be achieved for the target SVM training application as the cluster size increases. Hardware-software techniques that are crucial to achieve acceleration such as the management of data partition size are explored. We demonstrate the benefits of the proposed framework, while also illustrate the importance of careful hardware-software management to avoid excessive CPU-FPGA communication that can quickly diminish the benefits of FPGA acceleration.
Persistent Identifierhttp://hdl.handle.net/10722/263555
ISBN

 

DC FieldValueLanguage
dc.contributor.authorHo, MH-
dc.contributor.authorWang, M-
dc.contributor.authorNg, HC-
dc.contributor.authorSo, HKH-
dc.date.accessioned2018-10-22T07:40:50Z-
dc.date.available2018-10-22T07:40:50Z-
dc.date.issued2016-
dc.identifier.citation2016 International Conference on ReConFigurable Computing and FPGAs (ReConFig), Cancun, Mexico, 30 November-2 December 2016. In 2016 International Conference on ReConFigurable Computing and FPGAs (ReConFig), p. 1-6-
dc.identifier.isbn9781509037070-
dc.identifier.urihttp://hdl.handle.net/10722/263555-
dc.description.abstractA system that augments the Apache Spark data processing framework with FPGA accelerators is presented as a way to model and deploy FPGA-assisted applications in large-scale clusters. In our proposed framework, FPGAs can optionally be used in place of the host CPU for Resilient distributed datasets (RDDs) transformations, allowing seamless integration between gateware and software processing. Using the case of training an Support Vector Machine (SVM) cell image classifier as a case study, we explore the feasibilities, benefits and challenges of such technique. In our experiments where data communication between CPU and FPGA is tightly controlled, a consistent speedup of up to 1.6x can be achieved for the target SVM training application as the cluster size increases. Hardware-software techniques that are crucial to achieve acceleration such as the management of data partition size are explored. We demonstrate the benefits of the proposed framework, while also illustrate the importance of careful hardware-software management to avoid excessive CPU-FPGA communication that can quickly diminish the benefits of FPGA acceleration.-
dc.languageeng-
dc.publisherIEEE.-
dc.relation.ispartof2016 International Conference on ReConFigurable Computing and FPGAs (ReConFig16)-
dc.rights2016 International Conference on ReConFigurable Computing and FPGAs (ReConFig16). Copyright © IEEE.-
dc.subjectSupport vector machines-
dc.subjectSparks-
dc.subjectField programmable gate arrays-
dc.subjectTraining-
dc.subjectAcceleration-
dc.titleTowards FPGA-assisted spark: An SVM training acceleration case study-
dc.typeConference_Paper-
dc.identifier.emailSo, HKH: hso@eee.hku.hk-
dc.identifier.authoritySo, HKH=rp00169-
dc.description.naturelink_to_subscribed_fulltext-
dc.identifier.doi10.1109/ReConFig.2016.7857194-
dc.identifier.hkuros295142-
dc.identifier.spage1-
dc.identifier.epage6-

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