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Conference Paper: Architecture Generator for Type-3 Unum Posit Adder/Subtractor

TitleArchitecture Generator for Type-3 Unum Posit Adder/Subtractor
Authors
KeywordsUnum
Posit
FPGA
Multi-Precision
Digital Arithmetic
Issue Date2018
PublisherIEEE.
Citation
IEEE International Symposium on Circuits and Systems (ISCAS) 2018, Florence, Italy, 27-30 May 2018. In 2018 IEEE International Symposium on Circuits and Systems (ISCAS), p. 1-5 How to Cite?
AbstractThis paper is aimed towards the hardware architecture aspect of a recently proposed posit number system under type-3 unum (universal number system). Here, an algorithmic flow for the posit addition/subtraction arithmetic is developed and its hardware architecture is designed. Compare to floating point, posit provides better dynamic range and accuracy over same word size, along with more accurate and exact arithmetic support. Posit format includes a run-time varying exponent component, provided by a combination of regime-bits (of run-time varying length) and exponent-bits (of size up to ES bits). Thus, the mantissa precision also varies at run-time. This provides a combination of dynamic range and precision under a given word size (N). This possible variation in format along dynamic range and precision may attract various applications with different(accuracy and dynamic range) requirement. However, this run-time variation in posit format also poses a hardware design challenge. So, this paper is aimed towards the construction of an open-source parameterized Verilog HDL (Hardware Description Language) generator for posit adder/subtractor arithmetic, with parameterized N and ES.
DescriptionSession: Arithmetic Circuits & Systems II (Lecture), Track 2.1 Datapath & Arithmetic Circuits and Systems
Persistent Identifierhttp://hdl.handle.net/10722/263548
ISSN

 

DC FieldValueLanguage
dc.contributor.authorJaiswal, MK-
dc.contributor.authorSo, HKH-
dc.date.accessioned2018-10-22T07:40:43Z-
dc.date.available2018-10-22T07:40:43Z-
dc.date.issued2018-
dc.identifier.citationIEEE International Symposium on Circuits and Systems (ISCAS) 2018, Florence, Italy, 27-30 May 2018. In 2018 IEEE International Symposium on Circuits and Systems (ISCAS), p. 1-5-
dc.identifier.issn2379-447X-
dc.identifier.urihttp://hdl.handle.net/10722/263548-
dc.descriptionSession: Arithmetic Circuits & Systems II (Lecture), Track 2.1 Datapath & Arithmetic Circuits and Systems-
dc.description.abstractThis paper is aimed towards the hardware architecture aspect of a recently proposed posit number system under type-3 unum (universal number system). Here, an algorithmic flow for the posit addition/subtraction arithmetic is developed and its hardware architecture is designed. Compare to floating point, posit provides better dynamic range and accuracy over same word size, along with more accurate and exact arithmetic support. Posit format includes a run-time varying exponent component, provided by a combination of regime-bits (of run-time varying length) and exponent-bits (of size up to ES bits). Thus, the mantissa precision also varies at run-time. This provides a combination of dynamic range and precision under a given word size (N). This possible variation in format along dynamic range and precision may attract various applications with different(accuracy and dynamic range) requirement. However, this run-time variation in posit format also poses a hardware design challenge. So, this paper is aimed towards the construction of an open-source parameterized Verilog HDL (Hardware Description Language) generator for posit adder/subtractor arithmetic, with parameterized N and ES.-
dc.languageeng-
dc.publisherIEEE.-
dc.relation.ispartof2018 IEEE International Symposium on Circuits and Systems (ISCAS)-
dc.rights2018 IEEE International Symposium on Circuits and Systems (ISCAS). Copyright © IEEE.-
dc.rights©20xx IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.-
dc.subjectUnum-
dc.subjectPosit-
dc.subjectFPGA-
dc.subjectMulti-Precision-
dc.subjectDigital Arithmetic-
dc.titleArchitecture Generator for Type-3 Unum Posit Adder/Subtractor-
dc.typeConference_Paper-
dc.identifier.emailJaiswal, MK: manishkj@hku.hk-
dc.identifier.emailSo, HKH: hso@eee.hku.hk-
dc.identifier.authoritySo, HKH=rp00169-
dc.description.naturelink_to_subscribed_fulltext-
dc.identifier.doi10.1109/ISCAS.2018.8351142-
dc.identifier.hkuros294457-
dc.identifier.spage1-
dc.identifier.epage5-
dc.publisher.placeUnited States-

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