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Article: Area-efficient architectures for double precision multiplier on FPGA, with run-time-reconfigurable dual single precision support

TitleArea-efficient architectures for double precision multiplier on FPGA, with run-time-reconfigurable dual single precision support
Authors
Jaiswal, MKCheung, RCC
KeywordsArithmetic
Double precision
Floating point multiplication
FPGA
High performance computing
Karatsuba multiplication
Run-time-reconfigurable
Truncated block multiplier
Issue Date2013
Citation
Microelectronics Journal, 2013, v. 44, p. 421-430 How to Cite?
DOI: http://dx.doi.org/10.1016/j.mejo.2013.02.021
Persistent Identifierhttp://hdl.handle.net/10722/249998
ISI Accession Number ID
WOS:000318466900008

 

DC FieldValueLanguage
dc.contributor.authorJaiswal, MK-
dc.contributor.authorCheung, RCC-
dc.date.accessioned2017-12-20T09:19:10Z-
dc.date.available2017-12-20T09:19:10Z-
dc.date.issued2013-
dc.identifier.citationMicroelectronics Journal, 2013, v. 44, p. 421-430-
dc.identifier.urihttp://hdl.handle.net/10722/249998-
dc.languageeng-
dc.relation.ispartofMicroelectronics Journal-
dc.subjectArithmetic-
dc.subjectDouble precision-
dc.subjectFloating point multiplication-
dc.subjectFPGA-
dc.subjectHigh performance computing-
dc.subjectKaratsuba multiplication-
dc.subjectRun-time-reconfigurable-
dc.subjectTruncated block multiplier-
dc.titleArea-efficient architectures for double precision multiplier on FPGA, with run-time-reconfigurable dual single precision support-
dc.typeArticle-
dc.identifier.emailJaiswal, MK: manishkj@hku.hk-
dc.identifier.doi10.1016/j.mejo.2013.02.021-
dc.identifier.scopuseid_2-s2.0-84876298466-
dc.identifier.hkuros280310-
dc.identifier.volume44-
dc.identifier.spage421-
dc.identifier.epage430-
dc.identifier.isiWOS:000318466900008-

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