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Article: Improved Stability of α -InGaZnO Thin-Film Transistor under Positive Gate Bias Stress by Using Fluorine Plasma Treatment

TitleImproved Stability of α -InGaZnO Thin-Film Transistor under Positive Gate Bias Stress by Using Fluorine Plasma Treatment
Authors
Huang, XDSONG, JLai, PT
Keywordselectrical instability
fluorine treatment
high-k gate dielectric
InGaZnO (IGZO)
thin-film transistor (TFT)
Issue Date2017
PublisherIEEE. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=55
Citation
IEEE Electron Device Letters, 2017, v. 38, p. 576-579 How to Cite?
DOI: http://dx.doi.org/10.1109/LED.2017.2678468
Persistent Identifierhttp://hdl.handle.net/10722/247439
ISSN
0741-3106
2021 Impact Factor: 4.816
2020 SCImago Journal Rankings: 1.337
ISI Accession Number ID
WOS:000400413200011

 

DC FieldValueLanguage
dc.contributor.authorHuang, XD-
dc.contributor.authorSONG, J-
dc.contributor.authorLai, PT-
dc.date.accessioned2017-10-18T08:27:16Z-
dc.date.available2017-10-18T08:27:16Z-
dc.date.issued2017-
dc.identifier.citationIEEE Electron Device Letters, 2017, v. 38, p. 576-579-
dc.identifier.issn0741-3106-
dc.identifier.urihttp://hdl.handle.net/10722/247439-
dc.languageeng-
dc.publisherIEEE. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=55-
dc.relation.ispartofIEEE Electron Device Letters-
dc.rightsIEEE Electron Device Letters. Copyright © IEEE.-
dc.rights©20xx IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. -
dc.subjectelectrical instability-
dc.subjectfluorine treatment-
dc.subjecthigh-k gate dielectric-
dc.subjectInGaZnO (IGZO)-
dc.subjectthin-film transistor (TFT)-
dc.titleImproved Stability of α -InGaZnO Thin-Film Transistor under Positive Gate Bias Stress by Using Fluorine Plasma Treatment-
dc.typeArticle-
dc.identifier.emailLai, PT: laip@eee.hku.hk-
dc.identifier.authorityLai, PT=rp00130-
dc.identifier.doi10.1109/LED.2017.2678468-
dc.identifier.scopuseid_2-s2.0-85019204552-
dc.identifier.hkuros280921-
dc.identifier.volume38-
dc.identifier.spage576-
dc.identifier.epage579-
dc.identifier.isiWOS:000400413200011-
dc.publisher.placeUnited States-
dc.identifier.issnl0741-3106-

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