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Conference Paper: Taylor series based architecture for Quadruple Precision Floating Point Division

TitleTaylor series based architecture for Quadruple Precision Floating Point Division
Authors
KeywordsDigital Arithmetic
Floating Point Arithmetic
Division
FPGA
Iterative Architecture
FSM
Taylor Series Expansion Division
Issue Date2016
PublisherIEEE. The Journal's web site is located at http://ieeexplore.ieee.org/servlet/opac?punumber=1000807
Citation
The 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Pittsburgh, PA., 11-13 July 2016. In Conference Proceedings, 2016, p. 518-523 How to Cite?
AbstractThis paper presents an area efficient architecturefor quadruple precision division arithmetic on the FPGAplatform. Many application demands for the higher precisioncomputation (like quadruple precision) than the single anddouble precision. Division is an important arithmetic, butrequires a huge amount of hardware resources with increasingprecision, for a complete hardware implementation. So, thispaper presents an iterative architecture for quadruple precisiondivision arithmetic with small area requirement and promisingspeed. The implementation follows the standard processingsteps for the floating point division arithmetic, including processing of sub-normal operands and exceptional case handling. The most dominating part of the architecture, the mantissadivision, is based on the series expansion methodology ofdivision, and designed in an iterative fashion to minimize thehardware requirement. This unit requires a 114x114 bit integermultiplier, and thus, a FPGA based area-efficient integermultiplier is also proposed with better design metrics thanprior art on it. These proposed architectures are implementedon the Xilinx FPGA platform. The proposed quadruple precision division architecture shows a small hardware usage withpromising speed.
Persistent Identifierhttp://hdl.handle.net/10722/229798
ISSN

 

DC FieldValueLanguage
dc.contributor.authorJaiswal, MK-
dc.contributor.authorSo, HKH-
dc.date.accessioned2016-08-23T14:13:20Z-
dc.date.available2016-08-23T14:13:20Z-
dc.date.issued2016-
dc.identifier.citationThe 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Pittsburgh, PA., 11-13 July 2016. In Conference Proceedings, 2016, p. 518-523-
dc.identifier.issn2159-3477 (electronic)-
dc.identifier.urihttp://hdl.handle.net/10722/229798-
dc.description.abstractThis paper presents an area efficient architecturefor quadruple precision division arithmetic on the FPGAplatform. Many application demands for the higher precisioncomputation (like quadruple precision) than the single anddouble precision. Division is an important arithmetic, butrequires a huge amount of hardware resources with increasingprecision, for a complete hardware implementation. So, thispaper presents an iterative architecture for quadruple precisiondivision arithmetic with small area requirement and promisingspeed. The implementation follows the standard processingsteps for the floating point division arithmetic, including processing of sub-normal operands and exceptional case handling. The most dominating part of the architecture, the mantissadivision, is based on the series expansion methodology ofdivision, and designed in an iterative fashion to minimize thehardware requirement. This unit requires a 114x114 bit integermultiplier, and thus, a FPGA based area-efficient integermultiplier is also proposed with better design metrics thanprior art on it. These proposed architectures are implementedon the Xilinx FPGA platform. The proposed quadruple precision division architecture shows a small hardware usage withpromising speed.-
dc.languageeng-
dc.publisherIEEE. The Journal's web site is located at http://ieeexplore.ieee.org/servlet/opac?punumber=1000807-
dc.relation.ispartofIEEE Computer Society Annual Symposium on VLSI-
dc.rightsIEEE Computer Society Annual Symposium on VLSI. Copyright © IEEE.-
dc.rights©2016 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.-
dc.subjectDigital Arithmetic-
dc.subjectFloating Point Arithmetic-
dc.subjectDivision-
dc.subjectFPGA-
dc.subjectIterative Architecture-
dc.subjectFSM-
dc.subjectTaylor Series Expansion Division-
dc.titleTaylor series based architecture for Quadruple Precision Floating Point Division-
dc.typeConference_Paper-
dc.identifier.emailJaiswal, MK: manishkj@hku.hk-
dc.identifier.emailSo, HKH: hso@eee.hku.hk-
dc.identifier.authoritySo, HKH=rp00169-
dc.identifier.doi10.1109/ISVLSI.2016.10-
dc.identifier.hkuros261932-
dc.identifier.spage518-
dc.identifier.epage523-
dc.publisher.placeUnited States-
dc.customcontrol.immutablesml 160909-

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