File Download

There are no files associated with this item.

  Links for fulltext
     (May Require Subscription)
Supplementary

Conference Paper: Design of a DSP system based on FPGA

TitleDesign of a DSP system based on FPGA
Authors
KeywordsFPGA
Pipelining
DSP
Radix-4
Issue Date2011
Citation
Advanced Materials Research, 2011, v. 317-319, p. 1559-1562 How to Cite?
AbstractThis paper proposes an innovative methodology to design a DSP (Digital Signal Processing) system using FPGA (Field-programmable Gate Array). There are several main components in this system, including A/D sampling unit, FFT processing unit and control unit. A/D sampling and FFT processing units utilize the Nios processor in FPGA as controller. Control unit uses EP1C20 FPGA chip from ALTERA as FFT processing unit so as to manage the FIFO operations. This unit can handle 128 FFT operations. This system design approach is tested on Matlab. The results indicate that the calculation speed is much faster than common DSP manner. © (2011) Trans Tech Publications.
Persistent Identifierhttp://hdl.handle.net/10722/222116
ISSN
2015 SCImago Journal Rankings: 0.115

 

DC FieldValueLanguage
dc.contributor.authorHu, Ju Fang-
dc.contributor.authorXiong, Chun Ru-
dc.contributor.authorHu, Hao-
dc.contributor.authorZhong, Run Yang-
dc.date.accessioned2015-12-21T06:48:34Z-
dc.date.available2015-12-21T06:48:34Z-
dc.date.issued2011-
dc.identifier.citationAdvanced Materials Research, 2011, v. 317-319, p. 1559-1562-
dc.identifier.issn1022-6680-
dc.identifier.urihttp://hdl.handle.net/10722/222116-
dc.description.abstractThis paper proposes an innovative methodology to design a DSP (Digital Signal Processing) system using FPGA (Field-programmable Gate Array). There are several main components in this system, including A/D sampling unit, FFT processing unit and control unit. A/D sampling and FFT processing units utilize the Nios processor in FPGA as controller. Control unit uses EP1C20 FPGA chip from ALTERA as FFT processing unit so as to manage the FIFO operations. This unit can handle 128 FFT operations. This system design approach is tested on Matlab. The results indicate that the calculation speed is much faster than common DSP manner. © (2011) Trans Tech Publications.-
dc.languageeng-
dc.relation.ispartofAdvanced Materials Research-
dc.subjectFPGA-
dc.subjectPipelining-
dc.subjectDSP-
dc.subjectRadix-4-
dc.titleDesign of a DSP system based on FPGA-
dc.typeConference_Paper-
dc.description.natureLink_to_subscribed_fulltext-
dc.identifier.doi10.4028/www.scientific.net/AMR.317-319.1559-
dc.identifier.scopuseid_2-s2.0-80053124972-
dc.identifier.volume317-319-
dc.identifier.spage1559-
dc.identifier.epage1562-

Export via OAI-PMH Interface in XML Formats


OR


Export to Other Non-XML Formats