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Article: 3-D statistical simulation comparison of oxide reliability of planar MOSFETs and FinFET

Title3-D statistical simulation comparison of oxide reliability of planar MOSFETs and FinFET
Authors
Keywordsfully depleted silicon on insulator (FDSoI)
FinFET
Device modeling
variability
reliability
nanoscale MOSFETs
Issue Date2013
Citation
IEEE Transactions on Electron Devices, 2013, v. 60, n. 12, p. 4008-4013 How to Cite?
AbstractNew transistor architectures such as fully depleted silicon on insulator (FDSoI) MOSFETs and FinFETs have been introduced in advanced CMOS technology generations to boost performance and to reduce statistical variability (SV). In this paper, the robustness of these architectures to random telegraph noise and bias temperature instability issues is investigated using comprehensive 3-D numerical simulations, and results are compared with those obtained from conventional bulk MOSFETs. Not only the impact of static trapped charges is investigated, but also the charge trapping dynamics are studied to allow device lifetime and failure rate predictions. Our results show that device-to-device variability is barely increased by progressive oxide charge trapping in bulk devices. On the contrary, oxide degradation determines the SV of SoI and FinFET devices. However, the SoI and multigate transistor architectures are shown to be significantly more robust in terms of immunity to time-dependent SV when compared with the conventional bulk device. The comparative study here presented could be of significant importance for reliability resistant CMOS circuits and systems design. © 2013 IEEE.
Persistent Identifierhttp://hdl.handle.net/10722/221351
ISSN
2015 Impact Factor: 2.207
2015 SCImago Journal Rankings: 1.436
ISI Accession Number ID

 

DC FieldValueLanguage
dc.contributor.authorGerrer, Louis-
dc.contributor.authorAmoroso, Salvatore Maria-
dc.contributor.authorMarkov, Stanislav-
dc.contributor.authorAdamu-Lema, Fikru-
dc.contributor.authorAsenov, Asen-
dc.date.accessioned2015-11-18T06:09:04Z-
dc.date.available2015-11-18T06:09:04Z-
dc.date.issued2013-
dc.identifier.citationIEEE Transactions on Electron Devices, 2013, v. 60, n. 12, p. 4008-4013-
dc.identifier.issn0018-9383-
dc.identifier.urihttp://hdl.handle.net/10722/221351-
dc.description.abstractNew transistor architectures such as fully depleted silicon on insulator (FDSoI) MOSFETs and FinFETs have been introduced in advanced CMOS technology generations to boost performance and to reduce statistical variability (SV). In this paper, the robustness of these architectures to random telegraph noise and bias temperature instability issues is investigated using comprehensive 3-D numerical simulations, and results are compared with those obtained from conventional bulk MOSFETs. Not only the impact of static trapped charges is investigated, but also the charge trapping dynamics are studied to allow device lifetime and failure rate predictions. Our results show that device-to-device variability is barely increased by progressive oxide charge trapping in bulk devices. On the contrary, oxide degradation determines the SV of SoI and FinFET devices. However, the SoI and multigate transistor architectures are shown to be significantly more robust in terms of immunity to time-dependent SV when compared with the conventional bulk device. The comparative study here presented could be of significant importance for reliability resistant CMOS circuits and systems design. © 2013 IEEE.-
dc.languageeng-
dc.relation.ispartofIEEE Transactions on Electron Devices-
dc.rightsIEEE Transactions on Electron Devices. Copyright © IEEE.-
dc.rights©2013 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.-
dc.rightsCreative Commons: Attribution 3.0 Hong Kong License-
dc.subjectfully depleted silicon on insulator (FDSoI)-
dc.subjectFinFET-
dc.subjectDevice modeling-
dc.subjectvariability-
dc.subjectreliability-
dc.subjectnanoscale MOSFETs-
dc.title3-D statistical simulation comparison of oxide reliability of planar MOSFETs and FinFET-
dc.typeArticle-
dc.description.naturepublished_or_final_version-
dc.identifier.doi10.1109/TED.2013.2285588-
dc.identifier.scopuseid_2-s2.0-84889575741-
dc.identifier.hkuros234559-
dc.identifier.volume60-
dc.identifier.issue12-
dc.identifier.spage4008-
dc.identifier.epage4013-
dc.identifier.isiWOS:000327584400006-

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