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Conference Paper: New reliability mechanisms in memory design for sub-22nm technologies

TitleNew reliability mechanisms in memory design for sub-22nm technologies
Authors
Keywordsbulk-CMOS technology
DRAM
SRAM
sub-22nm technology nodes
Issue Date2011
Citation
Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011, 2011, p. 111-114 How to Cite?
AbstractThe TRAMS (Terascale Reliable Adaptive MEMORY Systems) project addresses in an evolutionary way the ultimate CMOS scaling technologies and paves the way for revolutionary, most promising beyond-CMOS technologies. In this abstract we show the significant variability levels of future 18 and 13nm device bulk-CMOS technologies as well as its dramatic effect on the yield of memory cells, and what kind of circuit solution would be required to maintain the current yield level. Later, we discuss the impact of errors at the system level, and different approaches at system level to adapt the heterogeneous systems to user's requirements. © 2011 IEEE.
Persistent Identifierhttp://hdl.handle.net/10722/221319

 

DC FieldValueLanguage
dc.contributor.authorAymerich, N.-
dc.contributor.authorAsenov, A.-
dc.contributor.authorBrown, A.-
dc.contributor.authorCanal, R.-
dc.contributor.authorCheng, B.-
dc.contributor.authorFigueras, J.-
dc.contributor.authorGonzalez, A.-
dc.contributor.authorHerrero, E.-
dc.contributor.authorMarkov, S.-
dc.contributor.authorMiranda, M.-
dc.contributor.authorPouyan, P.-
dc.contributor.authorRamirez, T.-
dc.contributor.authorRubio, A.-
dc.contributor.authorVatajelu, I.-
dc.contributor.authorVera, X.-
dc.contributor.authorWang, X.-
dc.contributor.authorZuber, P.-
dc.date.accessioned2015-11-18T06:08:59Z-
dc.date.available2015-11-18T06:08:59Z-
dc.date.issued2011-
dc.identifier.citationProceedings of the 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011, 2011, p. 111-114-
dc.identifier.urihttp://hdl.handle.net/10722/221319-
dc.description.abstractThe TRAMS (Terascale Reliable Adaptive MEMORY Systems) project addresses in an evolutionary way the ultimate CMOS scaling technologies and paves the way for revolutionary, most promising beyond-CMOS technologies. In this abstract we show the significant variability levels of future 18 and 13nm device bulk-CMOS technologies as well as its dramatic effect on the yield of memory cells, and what kind of circuit solution would be required to maintain the current yield level. Later, we discuss the impact of errors at the system level, and different approaches at system level to adapt the heterogeneous systems to user's requirements. © 2011 IEEE.-
dc.languageeng-
dc.relation.ispartofProceedings of the 2011 IEEE 17th International On-Line Testing Symposium, IOLTS 2011-
dc.subjectbulk-CMOS technology-
dc.subjectDRAM-
dc.subjectSRAM-
dc.subjectsub-22nm technology nodes-
dc.titleNew reliability mechanisms in memory design for sub-22nm technologies-
dc.typeConference_Paper-
dc.description.natureLink_to_subscribed_fulltext-
dc.identifier.doi10.1109/IOLTS.2011.5993820-
dc.identifier.scopuseid_2-s2.0-80052705929-
dc.identifier.spage111-
dc.identifier.epage114-

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