File Download
  Links for fulltext
     (May Require Subscription)
Supplementary

Conference Paper: Cache affinity optimization techniques for scaling software transactional memory systems on multi-CMP architectures

TitleCache affinity optimization techniques for scaling software transactional memory systems on multi-CMP architectures
Authors
KeywordsSoftware transactional memory
Concurrency control
Thread migration
Multicore processors
Cache affinity
Issue Date2015
PublisherIEEE. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=7164866
Citation
The 14th IEEE International Symposium on Parallel and Distributed Computing (ISPDC 2015), Limassol, Cyprus, 29 June-1 July 2015. In Conference Proceedings, 2015, p. 56-65 How to Cite?
AbstractSoftware transactional memory (STM) enhances both ease-of-use and concurrency, and is considered one of the next-generation paradigms for parallel programming. Application programs may see hotspots where data conflicts are intensive and seriously degrade the performance. So advanced STM systems employ dynamic concurrency control techniques to curb the conflict rate through properly throttling the rate of spawning transactions. High-end computers may have two or more multicore processors so that data sharing among cores goes through a non-uniform cache memory hierarchy. This poses challenges to concurrency control designs as improper metadata placement and sharing will introduce scalability issues to the system. Poor thread-to-core mappings that induce excessive cache invalidation are also detrimental to the overall performance. In this paper, we share our experience in designing and implementing a new dynamic concurrency controller for Tiny STM, which helps keeping the system concurrency at a near-optimal level. By decoupling unfavourable metadata sharing, our controller design avoids costly inter-processor communications. It also features an affinity-aware thread migration technique that fine-tunes thread placements by observing inter-thread transactional conflicts. We evaluate our implementation using the STAMP benchmark suite and show that the controller can bring around 21% average speedup over the baseline execution. © 2015 IEEE.
Persistent Identifierhttp://hdl.handle.net/10722/219217
ISBN

 

DC FieldValueLanguage
dc.contributor.authorChan, K-
dc.contributor.authorLam, KT-
dc.contributor.authorWang, CL-
dc.date.accessioned2015-09-18T07:18:00Z-
dc.date.available2015-09-18T07:18:00Z-
dc.date.issued2015-
dc.identifier.citationThe 14th IEEE International Symposium on Parallel and Distributed Computing (ISPDC 2015), Limassol, Cyprus, 29 June-1 July 2015. In Conference Proceedings, 2015, p. 56-65-
dc.identifier.isbn978-1-4673-7147-6-
dc.identifier.urihttp://hdl.handle.net/10722/219217-
dc.description.abstractSoftware transactional memory (STM) enhances both ease-of-use and concurrency, and is considered one of the next-generation paradigms for parallel programming. Application programs may see hotspots where data conflicts are intensive and seriously degrade the performance. So advanced STM systems employ dynamic concurrency control techniques to curb the conflict rate through properly throttling the rate of spawning transactions. High-end computers may have two or more multicore processors so that data sharing among cores goes through a non-uniform cache memory hierarchy. This poses challenges to concurrency control designs as improper metadata placement and sharing will introduce scalability issues to the system. Poor thread-to-core mappings that induce excessive cache invalidation are also detrimental to the overall performance. In this paper, we share our experience in designing and implementing a new dynamic concurrency controller for Tiny STM, which helps keeping the system concurrency at a near-optimal level. By decoupling unfavourable metadata sharing, our controller design avoids costly inter-processor communications. It also features an affinity-aware thread migration technique that fine-tunes thread placements by observing inter-thread transactional conflicts. We evaluate our implementation using the STAMP benchmark suite and show that the controller can bring around 21% average speedup over the baseline execution. © 2015 IEEE.-
dc.languageeng-
dc.publisherIEEE. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=7164866-
dc.relation.ispartofInternational Symposium on Parallel and Distributed Computing (ISPDC)-
dc.rightsInternational Symposium on Parallel and Distributed Computing (ISPDC). Copyright © IEEE.-
dc.rights©2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.-
dc.rightsThis work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License.-
dc.subjectSoftware transactional memory-
dc.subjectConcurrency control-
dc.subjectThread migration-
dc.subjectMulticore processors-
dc.subjectCache affinity-
dc.titleCache affinity optimization techniques for scaling software transactional memory systems on multi-CMP architectures-
dc.typeConference_Paper-
dc.identifier.emailLam, KT: kingtin@hku.hk-
dc.identifier.emailWang, CL: clwang@cs.hku.hk-
dc.identifier.authorityWang, CL=rp00183-
dc.description.naturepostprint-
dc.identifier.doi10.1109/ISPDC.2015.14-
dc.identifier.scopuseid_2-s2.0-84946059243-
dc.identifier.hkuros251501-
dc.identifier.spage56-
dc.identifier.epage65-
dc.publisher.placeUnited States-
dc.customcontrol.immutablesml 151214-

Export via OAI-PMH Interface in XML Formats


OR


Export to Other Non-XML Formats