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Conference Paper: Automatic Nested Loop Acceleration on FPGAs Using Soft CGRA Overlay

TitleAutomatic Nested Loop Acceleration on FPGAs Using Soft CGRA Overlay
Authors
Issue Date2015
Citation
2nd International Workshop on FPGAs for Software Programmers (FSP 2015), London, UK, 1 September 2015 How to Cite?
DescriptionSession 1: HLS Tooling
Persistent Identifierhttp://hdl.handle.net/10722/217365

 

DC FieldValueLanguage
dc.contributor.authorLiu, C-
dc.contributor.authorNg, HC-
dc.contributor.authorSo, HKH-
dc.date.accessioned2015-09-18T05:57:31Z-
dc.date.available2015-09-18T05:57:31Z-
dc.date.issued2015-
dc.identifier.citation2nd International Workshop on FPGAs for Software Programmers (FSP 2015), London, UK, 1 September 2015-
dc.identifier.urihttp://hdl.handle.net/10722/217365-
dc.descriptionSession 1: HLS Tooling-
dc.languageeng-
dc.relation.ispartofInternational Workshop on FPGAs for Software Programmers (FSP)-
dc.rightsCreative Commons: Attribution 3.0 Hong Kong License-
dc.titleAutomatic Nested Loop Acceleration on FPGAs Using Soft CGRA Overlay-
dc.typeConference_Paper-
dc.identifier.emailSo, HKH: skhay@hkucc.hku.hk-
dc.identifier.authoritySo, HKH=rp00169-
dc.description.naturepostprint-
dc.identifier.hkuros254000-
dc.publisher.placeUnited Kingdom-

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