File Download
  Links for fulltext
     (May Require Subscription)
Supplementary

Conference Paper: Latency-aware dynamic voltage and frequency scaling on many-core architectures for data-intensive applications

TitleLatency-aware dynamic voltage and frequency scaling on many-core architectures for data-intensive applications
Authors
KeywordsAlgorithm
Data-intensive
DVFS
Graph 500
Latency-aware
Power management
Issue Date2013
PublisherIEEE Computer Society. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/conhome.jsp?punumber=1803725
Citation
The 2013 International Conference on Cloud Computing and Big Data (Cloudcom-Asia 2013), Fuzhou, Fujian, China, 16-18 December 2013. In Conference Proceedings, 2013, p. 78-83 How to Cite?
AbstractLow power is an important design requirement for HPC systems nowadays. Dynamic voltage and frequency scaling (DVFS) has become the commonly used and efficient technology to achieve a trade-off between power consumption and system performance. However, most of the prior work using DVFS did not take into account the latency of voltage/frequency scaling, which is a critical factor in real hardware determining the efficiency of the power management algorithm. This paper investigates the latency aspects of DVFS on a real many-core hardware platform. We propose a latency-aware DVFS algorithm to achieve profile-guided power management to avoid aggressive power state transitions. We evaluate our algorithm on the Intel SCC platform using a data-intensive benchmark, Graph 500. The experimental results not only show impressive potential for energy saving in data-intensive applications (up to 31% energy saving and 60% EDP reduction), but also evaluate the efficiency of our latency-aware DVFS algorithm which achieves 12.0% extra energy saving and 5.0% extra EDP reduction, while increasing the execution performance by 22.4%. © 2014 IEEE.
Persistent Identifierhttp://hdl.handle.net/10722/203647
ISBN

 

DC FieldValueLanguage
dc.contributor.authorLai, Zen_US
dc.contributor.authorLam, KTen_US
dc.contributor.authorWang, CLen_US
dc.contributor.authorSu, Jen_US
dc.contributor.authorYan, Yen_US
dc.contributor.authorZhu, Wen_US
dc.date.accessioned2014-09-19T15:49:09Z-
dc.date.available2014-09-19T15:49:09Z-
dc.date.issued2013en_US
dc.identifier.citationThe 2013 International Conference on Cloud Computing and Big Data (Cloudcom-Asia 2013), Fuzhou, Fujian, China, 16-18 December 2013. In Conference Proceedings, 2013, p. 78-83en_US
dc.identifier.isbn978-1-4799-2829-3-
dc.identifier.urihttp://hdl.handle.net/10722/203647-
dc.description.abstractLow power is an important design requirement for HPC systems nowadays. Dynamic voltage and frequency scaling (DVFS) has become the commonly used and efficient technology to achieve a trade-off between power consumption and system performance. However, most of the prior work using DVFS did not take into account the latency of voltage/frequency scaling, which is a critical factor in real hardware determining the efficiency of the power management algorithm. This paper investigates the latency aspects of DVFS on a real many-core hardware platform. We propose a latency-aware DVFS algorithm to achieve profile-guided power management to avoid aggressive power state transitions. We evaluate our algorithm on the Intel SCC platform using a data-intensive benchmark, Graph 500. The experimental results not only show impressive potential for energy saving in data-intensive applications (up to 31% energy saving and 60% EDP reduction), but also evaluate the efficiency of our latency-aware DVFS algorithm which achieves 12.0% extra energy saving and 5.0% extra EDP reduction, while increasing the execution performance by 22.4%. © 2014 IEEE.en_US
dc.languageengen_US
dc.publisherIEEE Computer Society. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/conhome.jsp?punumber=1803725-
dc.relation.ispartofInternational Conference on Cloud Computing and Big Data (CloudCom-Asia) Proceedingsen_US
dc.rightsInternational Conference on Cloud Computing and Big Data (CloudCom-Asia). Copyright © IEEE Computer Society.-
dc.rights©2013 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.-
dc.rightsCreative Commons: Attribution 3.0 Hong Kong License-
dc.subjectAlgorithm-
dc.subjectData-intensive-
dc.subjectDVFS-
dc.subjectGraph 500-
dc.subjectLatency-aware-
dc.subjectPower management-
dc.titleLatency-aware dynamic voltage and frequency scaling on many-core architectures for data-intensive applicationsen_US
dc.typeConference_Paperen_US
dc.identifier.emailLai, Z: zqlai@hku.hken_US
dc.identifier.emailLam, KT: kingtin@hku.hken_US
dc.identifier.emailWang, CL: clwang@cs.hku.hken_US
dc.identifier.authorityWang, CL=rp00183en_US
dc.description.naturepublished_or_final_version-
dc.identifier.doi10.1109/CLOUDCOM-ASIA.2013.68-
dc.identifier.scopuseid_2-s2.0-84904549705-
dc.identifier.hkuros239053en_US
dc.identifier.spage78-
dc.identifier.epage83-
dc.publisher.placeUnited States-
dc.customcontrol.immutablesml 141003-

Export via OAI-PMH Interface in XML Formats


OR


Export to Other Non-XML Formats