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Conference Paper: A soft coarse-grained reconfigurable array based high-level synthesis methodology: Promoting design productivity and exploring extreme FPGA frequency

TitleA soft coarse-grained reconfigurable array based high-level synthesis methodology: Promoting design productivity and exploring extreme FPGA frequency
Authors
KeywordsCoarse-grained reconfigurable arrays
Design productivity
FPGA implementations
Hardware engineering
High level applications
High-level synthesis
Operation scheduling
Performance problems
Issue Date2013
PublisherIEEE Computer Society. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/conhome.jsp?punumber=1000289
Citation
The 21st Annual International IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2013), Seattle, WA., 28-30 April 2013. In Conference Proceedings, 2013, p. 228-228 How to Cite?
AbstractCompared to the use of a typical software development flow, the productivity of developing FPGA-based compute applications remains much lower. Although the use of high-level synthesis (HLS) tools may partly alleviate this shortcoming, the lengthy low-level FPGA implementation process remains a major obstacle to high productivity computing, limiting the number of compile-debug-edit cycles per day. Furthermore, high-level application developers often lack the intimate hardware engineering experience that is needed to achieve high performance on FPGAs, therefore undermining their usefulness as accelerators. To address the productivity and performance problems, a HLS methodology that utilizes soft coarse-grained reconfigurable arrays (SCGRAs) as an intermediate compilation step is presented. Instead of compiling high-level applications directly to circuits, the compilation process is reduced to an operation scheduling task targeting the SCGRA. © 2013 IEEE.
Persistent Identifierhttp://hdl.handle.net/10722/202275
ISBN
ISI Accession Number ID

 

DC FieldValueLanguage
dc.contributor.authorLiu, C-
dc.contributor.authorLin, CY-
dc.contributor.authorSo, HKH-
dc.date.accessioned2014-09-02T08:47:53Z-
dc.date.available2014-09-02T08:47:53Z-
dc.date.issued2013-
dc.identifier.citationThe 21st Annual International IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2013), Seattle, WA., 28-30 April 2013. In Conference Proceedings, 2013, p. 228-228-
dc.identifier.isbn978-0-7695-4969-9-
dc.identifier.urihttp://hdl.handle.net/10722/202275-
dc.description.abstractCompared to the use of a typical software development flow, the productivity of developing FPGA-based compute applications remains much lower. Although the use of high-level synthesis (HLS) tools may partly alleviate this shortcoming, the lengthy low-level FPGA implementation process remains a major obstacle to high productivity computing, limiting the number of compile-debug-edit cycles per day. Furthermore, high-level application developers often lack the intimate hardware engineering experience that is needed to achieve high performance on FPGAs, therefore undermining their usefulness as accelerators. To address the productivity and performance problems, a HLS methodology that utilizes soft coarse-grained reconfigurable arrays (SCGRAs) as an intermediate compilation step is presented. Instead of compiling high-level applications directly to circuits, the compilation process is reduced to an operation scheduling task targeting the SCGRA. © 2013 IEEE.-
dc.languageeng-
dc.publisherIEEE Computer Society. The Journal's web site is located at http://ieeexplore.ieee.org/xpl/conhome.jsp?punumber=1000289-
dc.relation.ispartofAnnual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM) Proceedings-
dc.rightsAnnual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM). Copyright © IEEE Computer Society.-
dc.rights©2013 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.-
dc.rightsCreative Commons: Attribution 3.0 Hong Kong License-
dc.subjectCoarse-grained reconfigurable arrays-
dc.subjectDesign productivity-
dc.subjectFPGA implementations-
dc.subjectHardware engineering-
dc.subjectHigh level applications-
dc.subjectHigh-level synthesis-
dc.subjectOperation scheduling-
dc.subjectPerformance problems-
dc.titleA soft coarse-grained reconfigurable array based high-level synthesis methodology: Promoting design productivity and exploring extreme FPGA frequencyen_US
dc.typeConference_Paperen_US
dc.identifier.emailSo, HKH: skhay@hkucc.hku.hk-
dc.description.naturepublished_or_final_version-
dc.identifier.doi10.1109/FCCM.2013.21-
dc.identifier.scopuseid_2-s2.0-84881129674-
dc.identifier.hkuros236890-
dc.identifier.spage228-
dc.identifier.epage228-
dc.identifier.isiWOS:000326442500040-
dc.publisher.placeUnited States-
dc.customcontrol.immutablesml 140902-

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